TMS320C6452 DSP DDR2 Memory Controller User's Guide Literature Number: SPRUF85 October 2007
SPRUF85 – October 2007 Submit Documentation Feedback
Contents Preface ............................................................................................................................... 6 1 Introduction................................................................................................................ 9 1.1 Purpose of the Peripheral ....................................................................................... 9 1.2 Features ....................................................................................................
List of Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 4 DDR2 Memory Controller Block Diagram ............................................................................... DDR2 Memory Controller Signals ........................................................................................ DDR2 MRS and EMRS Command ...................................................................................... Refresh Command ......................................................
List of Tables 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 DDR2 Memory Controller Signal Descriptions ......................................................................... DDR2 SDRAM Commands ............................................................................................... Truth Table for DDR2 SDRAM Commands ............................................................................ Addressable Memory Ranges ..........................................................
Preface SPRUF85 – October 2007 Read This First About This Manual This document describes the operation of the DDR2 Memory Controller in the TMS320C6452. Notational Conventions This document uses the following conventions. • Hexadecimal numbers are shown with the suffix h. For example, the following number is 40 hexadecimal (decimal 64): 40h. • Registers in this document are shown in figures and described in tables.
www.ti.com Related Documents From Texas Instruments SPRUF87 — TMS320C6452 DSP Host Port Interface (UHPI) User's Guide describes the host port interface (HPI) in the TMS320C6452 Digital Signal Processor (DSP). The HPI is a parallel port through which a host processor can directly access the CPU memory space. The host device functions as a master to the interface, which increases ease of access. The host and CPU can exchange information via internal or external memory.
www.ti.com Related Documents From Texas Instruments SPRUF97 — TMS320C6452 DSP 3 Port Switch (3PSW) Ethernet Subsystem User's Guide describes the operation of the 3 port switch (3PSW) ethernet subsystem in the TMS320C6452 Digital Signal Processor (DSP). The 3 port switch gigabit ethernet subsystem provides ethernet packet communication and can be configured as an ethernet switch.
User's Guide SPRUF85 – October 2007 DSP DDR2 Memory Controller 1 Introduction This document describes the DDR2 memory controller in the device. 1.1 Purpose of the Peripheral The DDR2 memory controller is used to interface with JESD79D-2A standard compliant DDR2 SDRAM devices. Memory types such as DDR1 SDRAM, SDR SDRAM, SBSRAM, and asynchronous memories are not supported. The DDR2 memory controller SDRAM can be used for program and data storage. 1.
www.ti.com Introduction Figure 1.
www.ti.com Peripheral Architecture 2 Peripheral Architecture The DDR2 memory controller can gluelessly interface to most standard DDR2 SDRAM devices and supports such features as self-refresh mode and prioritized refresh. In addition, it provides flexibility through programmable parameters such as the refresh rate, CAS latency, and many SDRAM timing parameters.
www.ti.com Peripheral Architecture Figure 2. DDR2 Memory Controller Signals DDR_CLK DDR_CLK DDR_CKE DDR_CS DDR_WE DDR_RAS DDR2 memory controller DDR_CAS DDR_DQM[3:0] DDR_DQS[3:0] DDR_DQS[3:0] DDR_BA[2:0] DDR_A[13:0] DDR_D[31:0] DDR_ODT[1:0] DDR_DQGATE[3:0] DDR_VREF Table 1. DDR2 Memory Controller Signal Descriptions 12 Pin Description DDR_D[31:0] Bidirectional data bus. Input for data reads and output for data writes. DDR_A[13:0] External address output.
www.ti.com Peripheral Architecture 2.4 Protocol Description(s) The DDR2 memory controller supports the DDR2 SDRAM commands listed in Table 2. Table 3 shows the signal truth table for the DDR2 SDRAM commands. Table 2. DDR2 SDRAM Commands Command Function ACTV Activates the selected bank and row. DCAB Precharge all command. Deactivates (precharges) all banks. DEAC Precharge single command. Deactivates (precharges) a single bank. DESEL Device Deselect. EMRS Extended Mode Register set.
www.ti.com Peripheral Architecture 2.4.1 Mode Register Set (MRS and EMRS) DDR2 SDRAM contains mode and extended mode registers that configure the DDR2 memory for operation. These registers control burst type, burst length, CAS latency, DLL enable/disable, single-ended strobe, etc. The DDR2 memory controller programs the mode and extended mode registers of the DDR2 memory by issuing MRS and EMRS commands.
www.ti.com Peripheral Architecture Figure 4. Refresh Command DDR_CLK DDR_CLK REFR DDR_CKE DDR_CS DDR_RAS DDR_CAS DDR_WE DDR_A[13:0] DDR_BA[2:0] DDR_DQM[3:0] 2.4.3 Activation (ACTV) The DDR2 memory controller automatically issues the activate (ACTV) command before a read or write to a closed row of memory. The ACTV command opens a row of memory, allowing future accesses (reads or writes) with minimum latency. The value of DDR_BA[2:0] selects the bank and the value of A[12:0] selects the row.
www.ti.com Peripheral Architecture 2.4.4 Deactivation (DCAB and DEAC) The precharge all banks command (DCAB) is performed after a reset to the DDR2 memory controller or following the initialization sequence. DDR2 SDRAMs also require this cycle prior to a refresh (REFR) and mode set register commands (MRS and EMRS). During a DCAB command, DDR_A[10] is driven high to ensure the deactivation of all banks. Figure 6 shows the timing diagram for a DCAB command. Figure 6.
www.ti.com Peripheral Architecture 2.4.5 READ Command Figure 8 shows the DDR2 memory controller performing a read burst from DDR2 SDRAM. The READ command initiates a burst read operation to an active row. During the READ command, DDR_CAS drives low, DDR_WE and DDR_RAS remain high, the column address is driven on DDR_A[12:0], and the bank address is driven on DDR_BA[2:0]. The DDR2 memory controller uses a burst length of 8, and has a programmable CAS latency of 2, 3, 4, or 5.
www.ti.com Peripheral Architecture 2.4.6 Write (WRT) Command Prior to a WRT command, the desired bank and row are activated by the ACTV command. Following the WRT command, a write latency is incurred. Write latency is equal to CAS latency minus 1. All writes have a burst length of 8. The use of the DDR_DQM outputs allows byte and halfword writes to be executed. Figure 9 shows the timing for a write on the DDR2 memory controller.
www.ti.com Peripheral Architecture Figure 10 shows the byte lanes used on the DDR2 memory controller. The external memory is always right aligned on the data bus. Figure 10. Byte Alignment DDR2 memory controller data bus DDR_D[23:16] (Byte Lane 2) DDR_D[31:24] (Byte Lane 3) DDR_D[15:8] (Byte Lane 1) DDR_D[7:0] (Byte Lane 0) 32-bit memory device 16-bit memory device 2.6 Address Mapping The DDR2 memory controller views external DDR2 SDRAM as one continuous block of memory.
www.ti.
www.ti.com Peripheral Architecture Figure 11 shows how the DSP memory map is partitioned into columns, rows, and banks. Note that during a linear access, the DDR2 memory controller increments the column address as the logical address increments. When the DDR2 memory controller reaches a page/row boundary, it moves onto the same page/row in the next bank. This movement continues until the same page has been accessed in all banks. To the DDR2 SDRAM, this process looks as shown on Figure 14.
www.ti.com Peripheral Architecture Figure 14. DDR2 SDRAM Column, Row, and Bank Access Bank 0 C C C o o o l l l 0 1 2 3 C o l M Row 0 Row 1 Row 2 Bank 1 Row 0 C C C o o o l l l 0 1 2 3 Row 1 Row 2 C o l M Bank 2 Row 0 Row 1 Row 2 C C C o o o l l l 0 1 2 3 C o l M Bank P Row 0 Row 1 Row N C C C o o o l l l 0 1 2 3 C o l M Row 2 Row N Row N Row N A 2.
www.ti.com Peripheral Architecture Figure 15. DDR2 Memory Controller FIFO Block Diagram Command FIFO Command/Data Scheduler Command to Memory EDMA BUS Write FIFO Write Data to Memory Read FIFO Read Data from Memory Registers Command Data 2.7.1 Command Ordering and Scheduling, Advanced Concept The DDR2 memory controller performs command re-ordering and scheduling in an attempt to achieve efficient transfers with maximum throughput.
www.ti.com Peripheral Architecture Next, the DDR2 memory controller examines each of the commands selected by the individual masters and performs the following reordering: • Among all pending reads, selects reads to rows already open. Among all pending writes, selects writes to rows already open. • Selects the highest priority command from pending reads and writes to open rows. If multiple commands have the highest priority, then the DDR2 memory controller selects the oldest command.
www.ti.com Peripheral Architecture 2.7.3 Possible Race Condition A race condition may exist when certain masters write data to the DDR2 memory controller. For example, if master A passes a software message via a buffer in DDR2 memory and does not wait for indication that the write completes, when master B attempts to read the software message it may read stale data and therefore receive an incorrect message.
www.ti.com Peripheral Architecture 2.9 Self-Refresh Mode Setting the self refresh (SR) bit in the SDRAM refresh control register (SDRFC) to 1 forces the DDR2 memory controller to place the external DDR2 SDRAM in a low-power mode (self refresh), in which the DDR2 SDRAM maintains valid data while consuming a minimal amount of power.
www.ti.com Peripheral Architecture 2.11 DDR2 SDRAM Memory Initialization DDR2 SDRAM devices contain mode and extended mode registers that configure the mode of operation for the device. These registers control parameters such as burst type, burst length, and CAS latency. The DDR2 memory controller programs the mode and extended mode registers of the DDR2 memory by issuing MRS and EMRS commands during the initialization sequence described in Section 2.11.2 and Section 2.11.3.
www.ti.com Peripheral Architecture Table 10. DDR2 SDRAM Extended Mode Register 1 Configuration (continued) 2.11.2 Mode Mode Register Register Bit Field Init Value Description 2 ODT Value (Rtt) 1 On-die termination effective resistance (Rtt) bits. Together with bit 2, this bit selects the value for Rtt as 75Ω. 1 Output Driver Impedance SDCFG.DDR_DRIVE Output driver impedance control bits. Initialized using the DDR_DRIVE bit of the SDRAM configuration register (SDCFG).
www.ti.com Using the DDR2 Memory Controller 3 Using the DDR2 Memory Controller The following sections show various ways to connect the DDR2 memory controller to DDR2 memory devices. The steps required to configure the DDR2 memory controller for external memory access are also described. 3.
www.ti.com Using the DDR2 Memory Controller Figure 17.
www.ti.com Using the DDR2 Memory Controller Figure 18.
www.ti.com Using the DDR2 Memory Controller Figure 19.
www.ti.com Using the DDR2 Memory Controller 3.2 Configuring DDR2 Memory Controller Registers to Meet DDR2 SDRAM Specifications The DDR2 memory controller allows a high degree of programmability for shaping DDR2 accesses. This provides the DDR2 memory controller with the flexibility to interface with a variety of DDR2 devices.
www.ti.com Using the DDR2 Memory Controller Table 12 displays the DDR2-533 refresh rate specification. Table 12. DDR2 Memory Refresh Specification Symbol Description Value tREF Average Periodic Refresh Interval 7.8 μs Therefore, the value for the REFRESH-RATE can be calculated as follows: REFRESH_RATE = 266.5 MHz × 7.8 μs = 2078.7 = 81Eh Table 13 shows the resulting SDRFC configuration. Table 13. SDRFC Configuration Field Value SR 0 REFRESH_RATE 3.2.
www.ti.com Using the DDR2 Memory Controller Table 15. SDTIM2 Configuration 3.2.
www.ti.com DDR2 Memory Controller Registers 4 DDR2 Memory Controller Registers Table 17 lists the memory-mapped registers for the DDR2 memory controller. See the device-specific data manual for the memory address of these registers. Table 17. DDR2 Memory Controller Registers Offset 36 Acronym Register Description 00h MIDR Module ID and Revision Register Section 4.1 04h DMCSTAT DDR2 Memory Controller Status Register Section 4.2 08h SDCFG SDRAM Configuration Register Section 4.
www.ti.com DDR2 Memory Controller Registers 4.1 Module ID and Revision Register (MIDR) The Module ID and Revision register (MIDR) is shown in Figure 20 and described in Table 18. Figure 20. Module ID and Revision Register (MIDR) 31 30 29 16 Reserved MOD_ID R-0x0 R-0x0031 15 8 7 0 MJ_REV MN_REV R-0x03 R-0x0F LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 18.
www.ti.com DDR2 Memory Controller Registers 4.3 SDRAM Configuration Register (SDCFG) The SDRAM configuration register (SDCFG) contains fields that program the DDR2 memory controller to meet the specification of the DDR2 memory. These fields configure the DDR2 memory controller to match the data bus width, CAS latency, number of internal banks, and page size of the external DDR2 memory. Bits 0-14 of the SDCFG register are only writeable when the TIMUNLOCK bit is set to 0 (unlocked). See Section 2.11.
www.ti.com DDR2 Memory Controller Registers Table 20. SDRAM Configuration Register (SDCFG) Field Descriptions (continued) Bit 11-9 Field Value CL Description CAS latency. The value of this field defines the CAS latency, to be used when accessing connected SDRAM devices. A write to this field will cause the DDR2 Memory Controller to start the SDRAM initialization sequence. This field is writeable only when the TIMUNLOCK bit is unlocked. Values 0, 1, 6, and 7 are reserved for this field.
www.ti.com DDR2 Memory Controller Registers 4.4 SDRAM Refresh Control Register (SDRFC) The SDRAM refresh control register (SDRFC) is used to configure the DDR2 memory controller to: • Enter and Exit the self-refresh state. • Meet the refresh requirement of the attached DDR2 device by programming the rate at which the DDR2 memory controller issues autorefresh commands. The SDRFC is shown in Figure 23 and described in Table 21. Figure 23.
www.ti.com DDR2 Memory Controller Registers 4.5 SDRAM Timing 1 Register (SDTIM1) The SDRAM timing 1 register (SDTIM1) configures the DDR2 memory controller to meet many of the AC timing specification of the DDR2 memory. Note that DDR_CLK is equal to the period of the DDR_CLK signal. See the DDR2 memory data sheet for information on the appropriate values to program each field.
www.ti.com DDR2 Memory Controller Registers Table 22. SDRAM Timing 1 Register (SDTIM1) Field Descriptions (continued) Bit Field 1-0 T_WTR Value Description These bits specify the minimum number of DDR_CLK cycles from the last write to a read command, minus 1. The value for these bits can be derived from the twtr AC timing parameter in the DDR2 memory data sheet.
www.ti.com DDR2 Memory Controller Registers 4.6 SDRAM Timing 2 Register (SDTIM2) Like the SDRAM timing 1 register (SDTIM1), the SDRAM timing 2 register (SDTIM2) also configures the DDR2 memory controller to meet the AC timing specification of the DDR2 memory. See the DDR2 memory data sheet for information on the appropriate values to program each field. The bit fields in the SDTIM2 register are only writeable when the TIMUNLOCK bit of the SDRAM Configuration register (SDCFG) is unlocked.
www.ti.com DDR2 Memory Controller Registers 4.7 Burst Priority Register (BPRIO) The Burst Priority Register (BPRIO) helps prevent command starvation within the DDR2 memory controller. To avoid command starvation, the DDR2 memory controller momentarily raises the priority of the oldest command in the command FIFO after a set number of transfers have been made. The PRIO_RAISE bit sets the number of transfers that must be made before the DDR2 memory controller raises the priority of the oldest command.
www.ti.com DDR2 Memory Controller Registers 4.8 DDR2 Memory Controller Control Register (DMCCTL) The DDR2 memory controller control register (DMCCTL) resets the interface logic of the DDR2 memory controller. The DMCCTL is shown in Figure 27 and described in Table 25. Figure 27.
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
