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AECLKOUT
ACEx
ABE[7:0]
AEA[19:0]/
ABA[1:0]
AED[63:0]
AAOE/ASOE
(A)
AR/W
AAWE/ASWE
(A)
AARDY
(B)
Byte Enables
Address
Write Data
Hold = 1
12
Strobe = 4
Setup = 1
12
12
12
12
13
13
11
11
11
11
11
A AAOE/ASOE and AAWE/ASWE operate as AAOE (identified under select signals) and AAWE, respectively, during asynchronous memory
accesses.
B Polarity of the AARDY signal is programmable through the AP field of the EMIFA Async Wait Cycle Configuration register (AWCC).
DEASSERTED
AECLKOUT
AARDY
(A)
ASSERTED DEASSERTED
Strobe
Hold = 2Extended Strobe
Strobe
Setup = 2
A Polarity of the AARDY signal is programmable through the AP field of the EMIFA Async Wait Cycle Configuration register (AWCC).
8
9
6
5
7
7
TMS320C6454
Fixed-Point Digital Signal Processor
SPRS311A – APRIL 2006 – REVISED DECEMBER 2006
Figure 7-34. Asynchronous Memory Write Timing for EMIFA
Figure 7-35. AARDY Timing
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