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RXD[3:0]
(A)
RXCTL
(A)
RXC
(at DSP)
(B)
5
RXERRRXDV
6
1st Half-byte
2nd Half-byte
RXD[7:4]RXD[3:0]
2
3
1
4
4
TMS320C6454
Fixed-Point Digital Signal Processor
SPRS311A – APRIL 2006 – REVISED DECEMBER 2006
Table 7-86. Timing Requirements for EMAC RGMII Input Receive for 10/100/1000 Mbps
(1)
(see Figure 7-69 )
-720
-850
NO. UNIT
-1000
MIN MAX
5 t
su(RXD-RXCH)
Setup time, receive selected signals valid before RXC (at DSP) high/low 1.0 ns
6 t
h(RXCH-RXD)
Hold time, receive selected signals valid after RXC (at DSP) high/low 1.0 ns
(1) For RGMII, receive selected signals include: RXD[3:0] and RXCTL.
A. Data and control information is received using both edges of the clocks. RXD[3:0] carries data bits 3-0 on the rising
edge of RXC and data bits 7-4 on the falling edge of RXC. Similarly, RXCTL carries RXDV on rising edge of RXC and
RXERR on falling edge
B. RXC must be externally delayed relative to the data and control pins.
Figure 7-69. EMAC Receive Interface Timing [RGMII Operation]
(A)(B)
Table 7-87. Switching Characteristics Over Recommended Operating Conditions for TXC - RGMII
Operation for 10/100/1000 Mbit/s (see Figure 7-70 )
-720
-850
NO. UNIT
-1000
MIN MAX
10 Mbps 360 440
1 t
c(TXC)
Cycle time, TXC 100 Mbps 36 44 ns
1000 Mbps 7.2 8.8
10 Mbps 0.40*t
c(TXC)
0.60*t
c(TXC)
2 t
w(TXCH)
Pulse duration, TXC high 100 Mbps 0.40*t
c(TXC)
0.60*t
c(TXC)
ns
1000 Mbps 0.45*t
c(TXC)
0.55*t
c(TXC)
10 Mbps 0.40*t
c(TXC)
0.60*t
c(TXC)
3 t
w(TXCL)
Pulse duration, TXC low 100 Mbps 0.40*t
c(TXC)
0.60*t
c(TXC)
ns
1000 Mbps 0.45*t
c(TXC)
0.55*t
c(TXC)
10 Mbps 0.75
4 t
t(TXC)
Transition time, TXC 100 Mbps 0.75 ns
1000 Mbps 0.75
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