Digital Signal Processor Product Preview

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PRODUCT PREVIEW
HD[15:0]/AD[15:0]
HR/W/PCBE2
HDS2/PCBE1
PCBE0/GP[2]
HHWIL/PCLK
HINT/PFRAME
PINTA/GP[14]
Data/Address
Arbitration
32
Clock
Control
PCI Interface
(A)
HAS/PPAR
PRST/GP[13]
HRDY/PIRDY
HCNTL0/PSTOP
PTRDY
PCBE3
PIDSEL
HCNTL1/PDEVSEL
HDS1/PSERR
Error
Command
Byte Enable
HCS/PPERR
PGNT/GP[12]
PREQ/GP[15]
HD[31:16]/AD[31:16]
A. These PCI pins are muxed with the HPI or GPIO peripherals. By default, these signals function as HPI or GPIO or EMAC. For more
details on these muxed pins, see the Device Configuration section of this document.
TMS320C6454
Fixed-Point Digital Signal Processor
SPRS311A – APRIL 2006 – REVISED DECEMBER 2006
Figure 2-11. PCI Peripheral Signals
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