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3.4.2 Peripheral Configuration Register 0 Description

TMS320C6454

Fixed-Point Digital Signal Processor

SPRS311A – APRIL 2006 – REVISED DECEMBER 2006

The Peripheral Configuration Register (PERCFG0) is used to change the state of the peripherals. One

write is allowed to this register within 16 SYSCLK3 cycles after the correct key is written to the PERLOCK

NOTE

The instructions that write to the PERLOCK and PERCFG0 registers must be in the same

fetch packet if code is being executed from external memory. If the instructions are in

different fetch packets, fetching the second instruction from external memory may stall the

instruction long enough such that PERCFG0 register will be locked before the instruction

is executed.

31 24

Reserved

R/W-0

23 21 20 19 18 17 16

Reserved PCICTL Reserved HPICTL Reserved McBSP1CTL

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

15 14 13 12 11 10 9 8

Reserved McBSP0CTL Reserved I2CCTL Reserved GPIOCTL Reserved TIMER0CTL

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

7 6 5 4 3 0

Reserved TIMER1CTL Reserved EMACCTL Reserved

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

LEGEND: R/W = Read/Write; - n = value after reset

Figure 3-4. Peripheral Configuration Register 0 (PERCFG0) - 0x02AC 0008

Table 3-7. Peripheral Configuration Register 0 (PERCFG0) Field Descriptions

Bit Field Value Description

31:21 Reserved Reserved.

20 PCICTL Mode control for PCI. This bit defaults to 1 when Host boot is used (BOOTMODE[3:0] = 0111b).

0 Set PCI to disabled mode

1 Set PCI to enabled mode

19 Reserved Reserved.

18 HPICTL Mode control for HPI. This bit defaults to 1 when Host boot is used (BOOTMODE[3:0] = 0001b).

0 Set HPI to disabled mode

1 Set HPI to enabled mode

17 Reserved 1 Reserved.

16 McBSP1CTL Mode control for McBSP1

0 Set McBSP1 to disabled mode

1 Set McBSP1 to enabled mode

15 Reserved Reserved.

14 McBSP0CTL Mode control for McBSP0

0 Set McBSP0 to disabled mode

1 Set McBSP0 to enabled mode

13 Reserved Reserved.

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