Digital Signal Processor Product Preview

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4K bytes
8K bytes
16K bytes
L1P memory
00E0 0000h
00E0 4000h
00E0 6000h
00E0 7000h
00E0 8000h
direct
mapped
SRAM
1/2
dm
3/4
SRAM
SRAM
7/8
All
SRAM
000 001 010 011 100
Block base
address
L1P mode bits
cache
4K bytes
cache
direct
mapped
cache
direct
mapped
cache
4K bytes
8K bytes
16K bytes
L1D memory
00F0 0000h
00F0 4000h
00F0 6000h
00F0 7000h
00F0 8000h
2-way
SRAM
1/2
2-way
3/4
SRAM
SRAM
7/8
All
SRAM
000 001 010 011 100
Block base
address
L1D mode bits
cache
4K bytes
cache
2-way
cache
2-way
cache
TMS320C6454
Fixed-Point Digital Signal Processor
SPRS311A – APRIL 2006 – REVISED DECEMBER 2006
• Region 1 size is 32K bytes with no wait states.
L1D is a two-way set-associative cache while L1P is a direct-mapped cache.
The L1P and L1D cache can be reconfigured via software through the L1PMODE field of the L1P
Configuration Register (L1PMODE) and the L1DMODE field of the L1D Configuration Register (L1DCFG)
of the C64x+ Megamodule. After device reset, L1P and L1D cache are configured as all cache or all
SRAM. The on-chip Bootloader changes the reset configuration for L1P and L1D. For more information,
see the TMS320C645x Bootloader User's Guide (literature number SPRUEC6 ).
Figure 5-2 and Figure 5-3 show the available SRAM/cache configurations for L1P and L1D, respectively.
Figure 5-2. TMS320C6454 L1P Memory Configurations
Figure 5-3. TMS320C6454 L1D Memory Configurations
C64x+ Megamodule78 Submit Documentation Feedback