Computer Hardware User Manual

Command/Data

Scheduler

Command FIFO

Write FIFO

Read FIFO

Registers

Command

to Memory

Write Data

to Memory

Read Data

from

Memory

Command

Data

EDMA BUS

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Peripheral Architecture

Figure 15. DDR2 Memory Controller FIFO Block Diagram

2.7.1 Command Ordering and Scheduling, Advanced Concept

The DDR2 memory controller performs command re-ordering and scheduling in an attempt to achieve

efficient transfers with maximum throughput. The goal is to maximize the utilization of the data, address,

and command buses while hiding the overhead of opening and closing DDR2 SDRAM rows. Command

re-ordering takes place within the command FIFO.

The DDR2 memory controller examines all the commands stored in the command FIFO to schedule

commands to the external memory. For each master, the DDR2 memory controller reorders the

commands based on the following rules:

• Selects the oldest command

• A read command is advanced before an older write command if the read is to a different block address

(2048 bytes) and the read priority is equal to or greater than the write priority.

NOTE: Most masters issue commands on a single priority level. Also, the EDMA transfer controller

read and write ports are considered different masters, and thus, the above rule does not

apply.

The second bullet above may be viewed as an exception to the first bullet. This means that for an

individual master, all of its commands will complete from oldest to newest, with the exception that a read

may be advanced ahead of an older, lower or equal priority write. Following this scheduling, each master

may have one command ready for execution.

SPRU970G– December 2005– Revised June 2011 C6455/C6454 DDR2 Memory Controller

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