User's Manual

7.1.3 Interleaver Data
7.1.3.1 ENDIAN_INTR = 1
www.ti.com Endianness
Figure 82. TCP_ENDIAN Register
31 16
Reserved
R/W
15 2 1 0
ENDIAN_ ENDIAN_
Reserved
EXTR INTR
R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; - n = value after reset
Table 33. TCP_ENDIAN Programming Register
Data Native Format DSP Memory Format TCP_ENDIAN
Interleaver Indexes 16 bits (15 bits right justified) 16 bits NATIVE ENDIAN_INTR = 1
Packed on 32 bits ENDIAN_INTR = 0
Extrinsic Data 8 bits (7 bits right justified 8 bits NATIVE ENDIAN_EXTR = 1
Packed on 32 bits ENDIAN_EXTR = 0
Table 34. Interleaver Data
Little_big_endian ENDIAN_INTR Description (MSB to LSB)
0 0 1,0,3,2 ⇒ 3,2,1,0 (half words)
0 1 0,1,2,3 ⇒ 3,2,1,0 (half words)
1 0 Endianness manager has no effect
3,2,1,0 ⇒ 3,2,1,0 (half words)
1 1 Endianness manager has no effect
3,2,1,0 ⇒ 3,2,1,0 (half words)
If ENDIAN_INTR = 1, data are saved in their native format (16 bits) in the DSP (see Table 35 ).
Table 35. Interleaver Indexes in DSP Memory
(ENDIAN_INTR = 1)
Address (hex bytes) Data
Base INTER0
Base + 2 INTER1
Base + 4 INTER2
Base + 6 INTER3
SPRUGK1 – March 2009 TMS320C6457 Turbo-Decoder Coprocessor 2 55
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