Incor User's Guide Ethernet Media Access Controller TMS320C645x DSP

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5.48 Transmit Channel 0-7 Completion Pointer Register (TX nCP)
EMAC Port Registers
The Transmit Channel 0-7 Completion Pointer Register (TX nCP) is shown in Figure 76 and described in
Table 76 .
Figure 76. Transmit Channel n Completion Pointer Register (TX nCP)
31 16
TX nCP
R/W-x
15 0
TX nCP
R/W-x
LEGEND: R/W = Read/Write; - n = value after reset
Table 76. Transmit Channel n Completion Pointer Register (TX nCP) Field Descriptions
Bit Field Value Description
31-0 TX nCP Transmit channel n completion pointer register is written by the host with the buffer descriptor
address for the last buffer processed by the host during interrupt processing. The EMAC uses the
value written to determine if the interrupt should be de-asserted.
Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)134 SPRU975B – August 2006
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