Incor User's Guide Ethernet Media Access Controller TMS320C645x DSP

www.ti.com
5.14 Receive Interrupt Status (Masked) Register (RXINTSTATMASKED)
EMAC Port Registers
The receive interrupt status (Masked) register (RXINTSTATMASKED) is shown in Figure 42 and
described in Table 42 .
Figure 42. Receive Interrupt Status (Masked) Register (RXINTSTATMASKED)
31 16
Reserved
R-0
15 8 7 6 5 4 3 2 1 0
Reserved RX7 RX6 RX5 RX4 RX3 RX2 RX1 RX0
PEND PEND PEND PEND PEND PEND PEND PEND
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
LEGEND: R = Read only; - n = value after reset
Table 42. Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) Field Descriptions
Bit Field Value Description
31-8 Reserved 0 Reserved
7 RX7PEND RX7PEND masked interrupt read
6 RX6PEND RX6PEND masked interrupt read
5 RX5PEND RX5PEND masked interrupt read
4 RX4PEND RX4PEND masked interrupt read
3 RX3PEND RX3PEND masked interrupt read
2 RX2PEND RX2PEND masked interrupt read
1 RX1PEND RX1PEND masked interrupt read
0 RX0PEND RX0PEND masked interrupt read
SPRU975B – August 2006 Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) 97
Submit Documentation Feedback