User's Guide

1 2 0 1 2 0
Prescalecounter
(TDDRHI)
Timercounter
(CNTHI)
15 16 0
32-bittimersettings:count=CNTHI=15;period=PRDHI=16
4-bitprescalersettings:count=TDDRHI=1;period=PSCHI=2
Timercounter
incremented
Prescalecounter
reset
Prescalecounter
reset
Timercounter
reset
www.ti.com Timer Modes
2.2.2.1 32-Bit Timer With a 4-Bit Prescaler (TIMHI)
In the unchained mode, the 4-bit prescaler must be clocked by the internal clock; an external clock source
cannot be used for TIMHI (except for C6472/TCI6486 devices). The 4-bit prescaler uses the timer
divide-down ratio bits (TDDRHI) and the prescale counter bits (PSCHI) in TCR to form a 4-bit prescale
counter register and a 4-bit prescale period register, respectively. When the timer is enabled, the prescale
counter starts incrementing by 1 at every timer input clock cycle. One cycle after the prescale counter
matches the prescale period, a clock signal is generated for the 32-bit timer.
The 32-bit timer uses the counter register (CNTHI) and the period register (PRDHI) to form a 32-bit timer
counter register and a 32-bit timer period register, respectively. The 32-bit timer is clocked by the output
clock from the 4-bit prescaler (see the example in Figure 7). When the timer is enabled, the timer counter
increments by 1 at every prescaler output clock cycle. When the timer counter matches the timer period, a
maskable timer interrupt (TINTHI) and a timer EDMA event (TEVTHI) are generated. The state of the
output signal is read in the timer status (TSTAT_HI) bit of the timer control register (TCR). When in pulse
mode (CP_HI = 0), TSTAT_HI stays high or low for 1, 2, 3, or 4 timer clock cycles. The pulse width
depends on the setting of the pulse width (PWID_HI) bits in TCR. When in clock mode (CP_HI = 1), the
TSTAT bit changes state (high-to-low or low-to-high) every time the timer counter matches the timer
period. When the timer is configured in continuous mode, the timer counter is reset to 0 on the cycle after
the timer counter reaches the timer period (see the example in Figure 7). The timer can be stopped,
restarted, reset, or disabled using TCR and the timer global control register (TGCR).
Figure 7. Dual 32-Bit Timers Unchained Mode Example
2.2.2.2 32-Bit Timer (TIMLO)
The other 32-bit timer (TIMLO) uses the counter register (CNTLO) and the period register (PRDLO) to
form a 32-bit timer counter register and a 32-bit timer period register, respectively. When the timer is
enabled, the timer counter increments by 1 at every timer input clock cycle. When the timer counter
matches the timer period, a maskable timer interrupt (TINTLO), a timer EDMA event (TEVTLO), and an
output signal (TOUTL) are generated; the state of the output signal is also read in the timer status
(TSTAT) bit of the timer control register (TCR). When in pulse mode (CP_LO = 0) and depending on the
timer output inverter control (INVOUTP) bit in TCR, the timer output pin (TOUTL) stays high or low for 1,
2, 3, or 4 timer clock cycles. The pulse width depends on the setting of the pulse width (PWID_LO) bits in
TCR. When in clock mode (CP_LO = 1), the timer output and the TSTAT_LO bit change state (high-to-low
or low-to-high) every time the timer counter matches the timer period. When the timer is configured in
continuous mode, the timer counter is reset to 0 on the cycle after the timer counter reaches the timer
period. The timer can be stopped, restarted, reset, or disabled using TCR and the timer global control
register (TGCR).
11
SPRU818B–December 2005–Revised September 2010 C6472/TCI648x 64-Bit Timer
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