User's Guide

INVINP
INVOUTP
TSTAT
CLKSRC
ENAMODE
Configuration
bus
Equal comparator
Count
enable
Timer period
register
Timer counter
register
CP
PWID (CP = 0)
Pulse generator
Internal clock
Gated
internal clock
TDDRHI bits
PSCHI bits
TINPL
TINPH (C6472/TCI6486 only)
TOUTL
External clock
Input clock
TIEN
0
1
0 1
TIMxxRS
Timer output
Interrupt to CPU
Event to EDMA controller
DSP
PLL1
controller
DSP inputclock
Internaltimerclock
Timer
Timer/prescaler
counter
www.ti.com Introduction to the Timer
Figure 1. Timer Block Diagram
The timer can be driven by an external clock at the timer input pin (TINPL) or by the divide-down clock
rate of the internal clock, as shown in Figure 2. For C6472/TCI6486 devices, TINPH can be used to drive
the higher 32-bit timer, TIMHI, in unchained mode. The internal clock is generated by the PLL1 controller
and is a divided-down version of the CPU clock. For more information, see the device-specific data
manual.
Figure 2. Generation of the Internal Timer Clock
7
SPRU818B–December 2005–Revised September 2010 C6472/TCI648x 64-Bit Timer
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