Floating Point Digital Signal Processor Specification Sheet

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SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005
52
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
PLL and PLL controller (continued)
OSCDIV1 Register (0x01B7 C124)
31
28 27
24 23 20 19
16
Reserved
R−0
15
14
12 11
87 54 3 21 0
OD1EN Reserved OSCDIV1
R/W−1 R−0 R/W−0 0111
Legend: R = Read only, R/W = Read/Write; -n = value after reset
The OSCDIV1 register controls the oscillator divider 1 for CLKOUT3. The CLKOUT3 signal does not go through
the PLL path.
Table 31. Oscillator Divider 1 Register (OSCDIV1)
BIT # NAME DESCRIPTION
31:16 Reserved Reserved. Read-only, writes have no effect.
15 OD1EN
Oscillator Divider 1 Enable.
0 – Oscillator Divider 1 Disabled.
1 – Oscillator Divider 1 Enabled (default).
14:5 Reserved Reserved. Read-only, writes have no effect.
4:0 OSCDIV1
Oscillator Divider 1 Ratio [default is /8 (0 0111)].
00000 = /1 10000 = /17
00001 = /2 10001 = /18
00010 = /3 10010 = /19
00011 = /4 10011 = /20
00100 = /5 10100 = /21
00101 = /6 10101 = /22
00110 = /7 10110 = /23
00111 = /8 10111 = /24
01000 = /9 11000 = /25
01001 = /10 11001 = /26
01010 = /11 11010 = /27
01011 = /12 11011 = /28
01100 = /13 11100 = /29
01101 = /14 11101 = /30
01110 = /15 11110 = /31
01111 = /16 11111 = /32