Floating Point Digital Signal Processor Specification Sheet


   
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005
67
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
INPUT AND OUTPUT CLOCKS
timing requirements for CLKIN
†‡§
(see Figure 21)
−150
NO
.
PLL MODE
(PLLEN = 1)
BYPASS MODE
(PLLEN = 0)
UNIT
MIN MAX MIN MAX
1 t
c(CLKIN)
Cycle time, CLKIN 6.7 83.3 6.7 ns
2 t
w(CLKINH)
Pulse duration, CLKIN high 0.4C 0.4C ns
3 t
w(CLKINL)
Pulse duration, CLKIN low 0.4C 0.4C ns
4 t
t(CLKIN)
Transition time, CLKIN 5 5 ns
†
The reference points for the rise and fall transitions are measured at V
IL
MAX and V
IH
MIN.
‡
C = CLKIN cycle time in ns. For example, when CLKIN frequency is 25 MHz, use C = 40 ns.
§
See the PLL and PLL Controller section of this data sheet.
CLKIN
1
2
3
4
4
Figure 21. CLKIN Timings
switching characteristics over recommended operating conditions for CLKOUT2
‡§
(see Figure 22)
NO.
PARAMETER
−150
UNIT
NO.
PARAMETER
MIN MAX
UNIT
1 t
c(CKO2)
Cycle time, CLKOUT2 C2 − 0.8 C2 + 0.8 ns
2 t
w(CKO2H)
Pulse duration, CLKOUT2 high (C2/2) − 0.8 (C2/2) + 0.8 ns
3 t
w(CKO2L)
Pulse duration, CLKOUT2 low (C2/2) − 0.8 (C2/2) + 0.8 ns
4 t
t(CKO2)
Transition time, CLKOUT2 2 ns
‡
The reference points for the rise and fall transitions are measured at V
OL
MAX and V
OH
MIN.
§
C2 = CLKOUT2 period in ns. CLKOUT2 period is determined by the PLL controller output SYSCLK2 period, which must be set to CPU period
divide-by-2.
CLKOUT2
1
2
3
4
4
Figure 22. CLKOUT2 Timings