Floating Point Digital Signal Processor Specification Sheet


   
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005
71
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ASYNCHRONOUS MEMORY TIMING (CONTINUED)
Setup = 2 Strobe = 3 Not Ready Hold = 2
BE
Address
Read Data
21
21
21
21
5
4
3
ARDY
77
66
5
ECLKOUT
CE[3:0]
EA[21:2]
ED[15:0]
AOE
/SDRAS/SSOE
†
ARE
/SDCAS/SSADS
†
BE[1:0]
AWE/SDWE/SSWE
†
†
AOE
/SDRAS/SSOE, ARE/SDCAS/SSADS, and AWE/SDWE/SSWE operate as AOE (identified under select signals), ARE, and AWE,
respectively, during asynchronous memory accesses.
Figure 26. Asynchronous Memory Read Timing