Floating Point Digital Signal Processor Specification Sheet


   
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005
76
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
SYNCHRONOUS DRAM TIMING (CONTINUED)
ECLKOUT
CE[3:0]
BE[1:0]
EA[11:2]
ED[15:0]
EA12
AOE
/SDRAS/SSOE
†
ARE/SDCAS/SSADS
†
AWE/SDWE/SSWE
†
EA[21:13]
BE1 BE2 BE3 BE4
Bank
Column
D1 D2 D3 D4
8
7
6
5
5
5
1
3
2
8
4
4
4
1
READ
†
ARE
/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM
accesses.
Figure 30. SDRAM Read Command (CAS Latency 3)