Floating Point Digital Signal Processor Specification Sheet

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   
SPRS293 − OCTOBER 2005
89
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
timing requirements for FSR when GSYNC = 1 (see Figure 42)
NO.
−150
UNIT
NO.
MIN MAX
UNIT
1 t
su(FRH-CKSH)
Setup time, FSR high before CLKS high 4 ns
2 t
h(CKSH-FRH)
Hold time, FSR high after CLKS high 4 ns
2
1
CLKS
FSR external
CLKR/X (no need to resync)
CLKR/X (needs resync)
Figure 42. FSR Timing When GSYNC = 1
timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0
†‡
(see Figure 43)
−150
NO.
MASTER SLAVE
UNIT
NO.
MIN MAX MIN MAX
UNIT
4 t
su(DRV-CKXL)
Setup time, DR valid before CLKX low 12 2 − 6P ns
5 t
h(CKXL-DRV)
Hold time, DR valid after CLKX low 4 5 + 12P ns
†
P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.7 ns.
‡
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.