Floating Point Digital Signal Processor Specification Sheet

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   
SPRS293 − OCTOBER 2005
97
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
JTAG TEST-PORT TIMING
timing requirements for JTAG test port (see Figure 49)
NO.
−150
UNIT
NO.
MIN MAX
UNIT
1 t
c(TCK)
Cycle time, TCK 35 ns
3 t
su(TDIV-TCKH)
Setup time, TDI/TMS/TRST valid before TCK high 10 ns
4 t
h(TCKH-TDIV)
Hold time, TDI/TMS/TRST valid after TCK high 7 ns
switching characteristics over recommended operating conditions for JTAG test port
(see Figure 49)
NO.
PARAMETER
−150
UNIT
NO.
PARAMETER
MIN MAX
UNIT
2 t
d(TCKL-TDOV)
Delay time, TCK low to TDO valid 0 15 ns
TCK
TDO
TDI/TMS/TRST
1
2
3
4
2
Figure 49. JTAG Test-Port Timing