Stereo System User Manual

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4.17 External Clock Input From Oscillator or CLKIN Pin
OSCV
DD
C
5
C
7
C
8
X
1
R
S
R
B
OSCIN
OSCOUT
C
6
OSCV
SS
CLKIN
Clock
Input
From
OSCIN
to
PLL
On-Chip 1.2-V Oscillator
(a)
External 3.3-V LVCMOS-Compatible Clock Source
(b)
OSCV
DD
OSCIN
OSCOUT
OSCV
SS
CLKIN
Clock
Input
From
CLKIN
to
PLL
CV
DD
(1.2 V)
NC
TMS320C6727, TMS320C6726, TMS320C6722
Floating-Point Digital Signal Processors
SPRS268E – MAY 2005 – REVISED JANUARY 2007
The C672x device includes two choices to provide an external clock input, which is fed to the on-chip PLL
to generate high-frequency system clocks. These options are illustrated in Figure 4-42 .
• Figure 4-42 (a) illustrates the option that uses an on-chip 1.2-V oscillator with external crystal circuit.
• Figure 4-42 (b) illustrates the option that uses an external 3.3-V LVCMOS-compatible clock input with
the CLKIN pin.
Note that the two clock inputs are logically combined internally before the PLL so the clock input that is not
used must be tied to ground.
Figure 4-42. C672x Clock Input Options
If the on-chip oscillator is chosen, then the recommended component values for Figure 4-42 (a) are listed
in Table 4-38 .
Table 4-38. Recommended On-Chip Oscillator Components
FREQUENCY XTAL TYPE X
1
C
5
(1)
C
6
(1)
C
7
C
8
R
B
R
S
22.579 AT-49 KDS 1AF225796A 470 pF 470 pF 8 pF 8 pF 1 M Ω 0 Ω
22.579 SMD-49 KDS 1AS225796AG 470 pF 470 pF 8 pF 8 pF 1 M Ω 0 Ω
24.576 AT-49 KDS 1AF245766AAA 470 pF 470 pF 8 pF 8 pF 1 M Ω 0 Ω
24.576 SMD-49 KDS 1AS245766AHA 470 pF 470 pF 8 pF 8 pF 1 M Ω 0 Ω
(1) Capacitors C
5
and C
6
are used to reduce oscillator jitter, but are optional. If C
5
and C
6
are not used, then the node connecting
capacitors C
7
and C
8
should be tied to OSCV
SS
and OSCV
DD
should be tied to CV
DD
.
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