Stereo System User Manual

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TMS320C6727, TMS320C6726, TMS320C6722
Floating-Point Digital Signal Processors
SPRS268E – MAY 2005 – REVISED JANUARY 2007
Table 2-12. Terminal Functions (continued)
GDH/
SIGNAL NAME RFP TYPE
(1)
PULL
(2)
GPIO
(3)
DESCRIPTION
ZDH
McASP0, McASP1, McASP2, and SPI1 Serial Ports
AHCLKR0/AHCLKR1 143 B3 IO - Y McASP0 and McASP1 Receive Master Clock
ACLKR0 139 A5 IO - Y McASP0 Receive Bit Clock
AFSR0 141 B4 IO - Y McASP0 Receive Frame Sync (L/R Clock)
AHCLKX0/AHCLKX2 2 C2 IO - Y McASP0 and McASP2 Transmit Master Clock
(4)
ACLKX0 142 A4 IO - Y McASP0 Transmit Bit Clock
AFSX0 144 A3 IO - Y McASP0 Transmit Frame Sync (L/R Clock)
AMUTE0 3 C1 O - Y McASP0 MUTE Output
AXR0[0] 113 A14 IO - Y McASP0 Serial Data 0
AXR0[1] 115 B13 IO - Y McASP0 Serial Data 1
AXR0[2] 116 A13 IO - Y McASP0 Serial Data 2
AXR0[3] 117 B12 IO - Y McASP0 Serial Data 3
AXR0[4] 119 A12 IO - Y McASP0 Serial Data 4
AXR0[5]/ SPI1_SCS 120 B11 IO - Y McASP0 Serial Data 5 or SPI1 Slave Chip Select
AXR0[6]/ SPI1_ENA 121 A11 IO - Y McASP0 Serial Data 6 or SPI1 Enable (Ready)
AXR0[7]/SPI1_CLK 122 B10 IO - Y McASP0 Serial Data 7 or SPI1 Serial Clock
AXR0[8]/AXR1[5]/ McASP0 Serial Data 8 or McASP1 Serial Data 5 or SPI1
126 B9 IO - Y
SPI1_SOMI Data Pin Slave Out Master In
AXR0[9]/AXR1[4]/ McASP0 Serial Data 9 or McASP1 Serial Data 4 or SPI1
127 A9 IO - Y
SPI1_SIMO Data Pin Slave In Master Out
AXR0[10]/AXR1[3] 130 B8 IO - Y McASP0 Serial Data 10 or McASP1 Serial Data 3
AXR0[11]/AXR1[2] 131 A8 IO - Y McASP0 Serial Data 11 or McASP1 Serial Data 2
AXR0[12]/AXR1[1] 134 B7 IO - Y McASP0 Serial Data 12 or McASP1 Serial Data 1
AXR0[13]/AXR1[0] 135 B6 IO - Y McASP0 Serial Data 13 or McASP1 Serial Data 0
AXR0[14]/AXR2[1] 137 A6 IO - Y McASP0 Serial Data 14 or McASP2 Serial Data 1
(4)
AXR0[15]/AXR2[0] 138 B5 IO - Y McASP0 Serial Data 15 or McASP2 Serial Data 0
(4)
ACLKR1 9 E1 IO - Y McASP1 Receive Bit Clock
AFSR1 12 F1 IO - Y McASP1 Receive Frame Sync (L/R Clock)
AHCLKX1 5 D1 IO - Y McASP1 Transmit Master Clock
ACLKX1 7 E2 IO - Y McASP1 Transmit Bit Clock
AFSX1 11 F2 IO - Y McASP1 Transmit Frame Sync (L/R Clock)
AMUTE1 4 D2 O - Y McASP1 MUTE Output
AHCLKR2 - C14 IO IPD Y McASP2 Receive Master Clock
ACLKR2 - C13 IO IPD Y McASP2 Receive Bit Clock
AFSR2 - C12 IO IPD Y McASP2 Receive Frame Sync (L/R Clock)
ACLKX2 - D11 IO IPD Y McASP2 Transmit Bit Clock
AFSX2 - C11 IO IPD Y McASP2 Transmit Frame Sync (L/R Clock)
AMUTE2/ HINT - D10 O IPD Y McASP2 MUTE Output or UHPI Host Interrupt
SPI0, I2C0, and I2C1 Serial Port Pins
SPI0_SOMI/I2C0_SDA 111 B14 IO - Y SPI0 Data Pin Slave Out Master In or I2C0 Serial Data
SPI0_SIMO 110 B15 IO - Y SPI0 Data Pin Slave In Master Out
SPI0_CLK/I2C0_SCL 108 C16 IO - Y SPI0 Serial Clock or I2C0 Serial Clock
SPI0_SCS/I2C1_SCL 107 C15 IO - Y SPI0 Slave Chip Select or I2C1 Serial Clock
SPI0_ENA/I2C1_SDA 105 D16 IO - Y SPI0 Enable (Ready) or I2C1 Serial Data
(4) McASP2 is not available on the C6722.
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