Stereo System User Manual

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TMS320C6727, TMS320C6726, TMS320C6722
Floating-Point Digital Signal Processors
SPRS268E – MAY 2005 – REVISED JANUARY 2007
Table 4-2 lists how the synchronization events are associated with event numbers in the dMAX controller.
Table 4-2. dMAX Peripheral Event Input Assignments
EVENT NUMBER EVENT ACRONYM EVENT DESCRIPTION
0 DETR[0] The CPU triggers the event by creating appropriate transition (edge) on bit0
in DETR register.
1 DETR[16] The CPU triggers the event by creating appropriate transition (edge) on bit16
in DETR register.
2 RTIREQ0 RTI DMA REQ[0]
3 RTIREQ1 RTI DMA REQ[1]
4 MCASP0TX McASP0 TX DMA REQ
5 MCASP0RX McASP0 RX DMA REQ
6 MCASP1TX McASP1 TX DMA REQ
7 MCASP1RX McASP1 RX DMA REQ
8 MCASP2TX McASP2 TX DMA REQ
9 MCASP2RX McASP2 RX DMA REQ
10 DETR[1] The CPU triggers the event by creating appropriate transition (edge) on bit1
in DETR register.
11 DETR[17] The CPU triggers the event by creating appropriate transition (edge) on bit17
in DETR register.
12 UHPIINT UHPI CPU_INT
13 SPI0RX SPI0 DMA_RX_REQ
14 SPI1RX SPI1 DMA_RX_REQ
15 RTIREQ2 RTI DMA REQ[2]
16 RTIREQ3 RTI DMA REQ[3]
17 DETR[2] The CPU triggers the event by creating appropriate transition (edge) on bit2
in DETR register.
18 DETR[18] The CPU triggers the event by creating appropriate transition (edge) on bit18
in DETR register.
19 I2C0XEVT I2C 0 Transmit Event
20 I2C0REVT I2C 0 Receive Event
21 I2C1XEVT I2C 1 Transmit Event
22 I2C1REVT I2C 1 Receive Event
23 DETR[3] The CPU triggers the event by creating appropriate transition (edge) on bit3
in DETR register.
24 DETR[19] The CPU triggers the event by creating appropriate transition (edge) on bit19
in DETR register.
25 Reserved
26 MCASP0ERR AMUTEIN0 or McASP0 TX INT or McASP0 RX INT (error on McASP0)
27 MCASP1ERR AMUTEIN1 or McASP1 TX INT or McASP1 RX INT (error on McASP1)
28 MCASP2ERR AMUTEIN2 or McASP2 TX INT or McASP2 RX INT (error on McASP2)
29 OVLREQ[0/1] Error on RTI
30 DETR[20] The CPU triggers the event by creating appropriate transition (edge) on bit20
in DETR register.
31 DETR[21] The CPU triggers the event by creating appropriate transition (edge) on bit21
in DETR register.
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