Stereo System User Manual

www.ti.com
4.11.3 EMIF Electrical Data/Timing
TMS320C6727, TMS320C6726, TMS320C6722
Floating-Point Digital Signal Processors
SPRS268E – MAY 2005 – REVISED JANUARY 2007
Table 4-5 through Table 4-8 assume testing over recommended operating conditions (see Figure 4-7
through Figure 4-13 ).
Table 4-5. EMIF SDRAM Interface Timing Requirements
NO. MIN MAX UNIT
19 t
su(EM_DV-EM_CLKH)
Input setup time, read data valid on D[31:0] before EM_CLK rising 3 ns
20 t
h(EM_CLKH-EM_DIV)
Input hold time, read data valid on D[31:0] after EM_CLK rising 1.9 ns
Table 4-6. EMIF SDRAM Interface Switching Characteristics
NO. PARAMETER MIN MAX UNIT
1 t
c(EM_CLK)
Cycle time, EMIF clock EM_CLK 10 ns
2 t
w(EM_CLK)
Pulse width, EMIF clock EM_CLK high or low 3 ns
3 t
d(EM_CLKH-EM_CSV)S
Delay time, EM_CLK rising to EM_CS[0] valid 7.7 ns
4 t
oh(EM_CLKH-EM_CSIV)S
Output hold time, EM_CLK rising to EM_CS[0] invalid 1.15 ns
5 t
d(EM_CLKH-EM_WE-DQMV)S
Delay time, EM_CLK rising to EM_ WE_DQM[3:0] valid 7.7 ns
6 t
oh(EM_CLKH-EM_WE-DQMIV)S
Output hold time, EM_CLK rising to EM_ WE_DQM[3:0] invalid 1.15 ns
7 t
d(EM_CLKH-EM_AV)S
Delay time, EM_CLK rising to EM_A[12:0] and EM_BA[1:0] valid 7.7 ns
Output hold time, EM_CLK rising to EM_A[12:0] and EM_BA[1:0]
8 t
oh(EM_CLKH-EM_AIV)S
1.15 ns
invalid
9 t
d(EM_CLKH-EM_DV)S
Delay time, EM_CLK rising to EM_D[31:0] valid 7.7 ns
10 t
oh(EM_CLKH-EM_DIV)S
Output hold time, EM_CLK rising to EM_D[31:0] invalid 1.15 ns
11 t
d(EM_CLKH-EM_RASV)S
Delay time, EM_CLK rising to EM_RAS valid 7.7 ns
12 t
oh(EM_CLKH-EM_RASIV)S
Output hold time, EM_CLK rising to EM_RAS invalid 1.15 ns
13 t
d(EM_CLKH-EM_CASV)S
Delay time, EM_CLK rising to EM_CAS valid 7.7 ns
14 t
oh(EM_CLKH-EM_CASIV)S
Output hold time, EM_CLK rising to EM_CAS invalid 1.15 ns
15 t
d(EM_CLKH-EM_WEV)S
Delay time, EM_CLK rising to EM_WE valid 7.7 ns
16 t
oh(EM_CLKH-EM_WEIV)S
Output hold time, EM_CLK rising to EM_WE invalid 1.15 ns
17 t
dis(EM_CLKH-EM_DHZ)S
Delay time, EM_CLK rising to EM_D[31:0] 3-stated 7.7 ns
18 t
ena(EM_CLKH-EM_DLZ)S
Output hold time, EM_CLK rising to EM_D[31:0] driving 1.15 ns
Submit Documentation Feedback Peripheral and Electrical Specifications 49