Stereo System User Manual

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1.3 Functional Block Diagram
Program/Data
RAM
256K Bytes
256
256
Program/Data
ROM Page0
256K Bytes
256
Program/Data
ROM Page1
128K Bytes
3232
DMPPMP
CSP 32
256
32K Bytes
Program
Cache
64
D1
Data
R/W
R/W
Data
D2
64
256
Program
FetchINTI/O
C67x+ CPU
Memory
Controller
32
High-Performance
Crossbar Switch
32
McASP DMA Bus
JTAG EMU
32
32
32
32
32
32
32
32
Peripheral Configuration Bus
EMIF
32
Events
In
32
MAX1MAX0
32
CONTROL
32
Interrupts
Out
I/O
dMAX
McASP0
16 Serializers
McASP1
6 Serializers
McASP2
2 Serializers
+ DIT
SPI1
SPI0
I2C1
I2C0
RTI32
UHPI
PLL
Peripheral Interrupt and DMA Events
32
32
32
32
32
TMS320C6727, TMS320C6726, TMS320C6722
Floating-Point Digital Signal Processors
SPRS268E – MAY 2005 – REVISED JANUARY 2007
Figure 1-1 shows the functional block diagram of the C672x device.
A. UHPI is available only on the C6727. McASP2 is not available on the C6722.
Figure 1-1. C672x DSP Block Diagram
Submit Documentation Feedback TMS320C6727, TMS320C6726, TMS320C6722 DSPs 5