Stereo System User Manual

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TMS320C6727, TMS320C6726, TMS320C6722

Floating-Point Digital Signal Processors

SPRS268E – MAY 2005 – REVISED JANUARY 2007

The UHPI has several device-level configuration registers which affect its behavior. Figure 4-18 ,

Figure 4-19 , and Figure 4-20 show the bit layout of these registers. Table 4-12 , Table 4-13 , and

Table 4-14 contain a description of the bits in these registers.

31 8

Reserved

7 5 4 3 2 1 0

Reserved BYTEAD FULL NMUX PAGEM ENA

R/W, 0 R/W, 0 R/W, 0 R/W, 0 R/W, 0

LEGEND: R/W = Read/Write; R = Read only; - n = value after reset

Figure 4-18. CFGHPI Register Bit Layout (0x4000 0008)

Table 4-12. CFGHPI Register Bit Field Description (0x4000 0008)

RESET READ

BIT NO. NAME DESCRIPTION

VALUE WRITE

31:5 Reserved N/A N/A Reads are indeterminate. Only 0s should be written to these bits.

4 BYTEAD 0 R/W UHPI Host Address Type

0 = Host Address is a word address

1 = Host Address is a byte address

3 FULL 0 R/W UHPI Multiplexing Mode (when NMUX = 0)

0 = Half-Word (16-bit data) Multiplexed Address and Data Mode

1 = Fullword (32-bit data) Multiplexed Address and Data Mode

2 NMUX 0 R/W UHPI Non-Multiplexed Mode Enable

0 = Multiplexed Address and Data Mode

1 = Non-Multiplexed Address and Data Mode (utilizes optional UHPI_HA[15:0] pins).

Host data bus is 32 bits in Non-Multiplexed mode. Setting this bit prevents the EMIF

from driving data out or 'parking' the shared EM_D[31:16]/UHPI_HA[15:0] pins.

1 PAGEM 0 R/W UHPI Page Mode Enable (Only for Multiplexed Address and Data Mode).

0 = Full 32-bit DSP address specified through host port.

1 = Only lower 16 bits of DSP address are specified through host port. Upper 16 bits

are restricted to the page selected by CFGHPIAMSB and CFGHPIAUMB registers.

0 ENA 0 R/W UHPI Enable

0 = UHPI is disabled

1 = UHPI is enabled. Set this bit to '1' only after configuring the other bits in this

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