Stereo System User Manual

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TMS320C6727, TMS320C6726, TMS320C6722
Floating-Point Digital Signal Processors
SPRS268E – MAY 2005 – REVISED JANUARY 2007
Table 4-23. McASP Switching Characteristics
(1)
NO. PARAMETER MIN MAX UNIT
Cycle time, AHCLKR internal, AHCLKR output 20
Cycle time, AHCLKR external, AHCLKR output 20
9 t
c(AHCKRX)
ns
Cycle time, AHCLKX internal, AHCLKX output 20
Cycle time, AHCLKX external, AHCLKX output 20
Pulse duration, AHCLKR internal, AHCLKR output (AHR/2) – 2.5
(2)
Pulse duration, AHCLKR external, AHCLKR output (AHR/2) – 2.5
(2)
10 t
w(AHCKRX)
ns
Pulse duration, AHCLKX internal, AHCLKX output (AHX/2) – 2.5
(3)
Pulse duration, AHCLKX external, AHCLKX output (AHX/2) – 2.5
(3)
Cycle time, ACLKR internal, ACLKR output greater of 2P or 20 ns
(4)
Cycle time, ACLKR external, ACLKR output greater of 2P or 20 ns
(4)
11 t
c(ACKRX)
ns
Cycle time, ACLKX internal, ACLKX output greater of 2P or 20 ns
(4)
Cycle time, ACLKX external, ACLKX output greater of 2P or 20 ns
(4)
Pulse duration, ACLKR internal, ACLKR output (AR/2) – 2.5
(5)
Pulse duration, ACLKR external, ACLKR output (AR/2) – 2.5
(5)
12 t
w(ACKRX)
ns
Pulse duration, ACLKX internal, ACLKX output (AX/2) – 2.5
(6)
Pulse duration, ACLKX external, ACLKX output (AX/2) – 2.5
(6)
Delay time, ACLKR internal, AFSR output 5
Delay time, ACLKX internal, AFSX output 5
Delay time, ACLKR external input, AFSR output 10
Delay time, ACLKX external input, AFSX output 10
Delay time, ACLKR external output, AFSR output 10
Delay time, ACLKX external output, AFSX output 10
13 t
d(ACKRX-FRX)
ns
Delay time, ACLKR internal, AFSR output –1
Delay time, ACLKX internal, AFSX output –1
Delay time, ACLKR external input, AFSR output 0
Delay time, ACLKX external input, AFSX output 0
Delay time, ACLKR external output, AFSR output 0
Delay time, ACLKX external output, AFSX output 0
Delay time, ACLKX internal, AXRn output –1 5
14 t
d(ACLKX-AXRV)
Delay time, ACLKX external input, AXRn output 0 10 ns
Delay time, ACLKX external output, AXRn output 0 10
Disable time, ACLKX internal, AXRn output –3 10
15 t
dis(ACKX-AXRHZ)
Disable time, ACLKX external input, AXRn output –3 10 ns
Disable time, ACLKX external output, AXRn output –3 10
(1) ACLKX internal – ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
ACLKX external input – ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
ACLKX external output – ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
ACLKR internal – ACLKRCTL.CLKRM = 1, PDIR.ACLKR =1
ACLKR external input – ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
ACLKR external output – ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
(2) AHR - Cycle time, AHCLKR.
(3) AHX - Cycle time, AHCLKX.
(4) P = SYSCLK2 period
(5) AR - ACLKR period.
(6) AX - ACLKX period.
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