Stereo System User Manual

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8
7
4
4
3
2
21
A0 A1 B0 B1A30 A31 B30 B31 C0 C1 C2 C3 C31
AHCLKR/X (Falling Edge Polarity)
AHCLKR/X (Rising Edge Polarity)
AFSR/X (Bit Width, 0 Bit Delay)
AFSR/X (Bit Width, 1 Bit Delay)
AFSR/X (Bit Width, 2 Bit Delay)
AFSR/X (Slot Width, 0 Bit Delay)
AFSR/X (Slot Width, 1 Bit Delay)
AFSR/X (Slot Width, 2 Bit Delay)
AXR[n] (Data In/Receive)
6
5
ACLKR/X (CLKRP = CLKXP = 0)
(A)
ACLKR/X (CLKRP = CLKXP = 1)
(B)
TMS320C6727, TMS320C6726, TMS320C6722
Floating-Point Digital Signal Processors
SPRS268E – MAY 2005 – REVISED JANUARY 2007
A. For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP
receiver is configured for falling edge (to shift data in).
B. For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP
receiver is configured for rising edge (to shift data in).
Figure 4-29. McASP Input Timings
Peripheral and Electrical Specifications78 Submit Documentation Feedback