Universal Serial Bus OHCI Host Controller User's Guide

3 Registers
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Most of the host controller (HC) registers are OHCI operational registers, defined by the OHCI
Specification for USB. Four additional registers not specified by the OHCI Specification for USB provide
additional information about the USB host controller state. USB host controller registers can be accessed
in user and supervisor modes.
To enhance code reusability with possible future versions of the USB host controller, reads and writes to
reserved USB host controller register addresses are to be avoided. Unless otherwise specified, when
writing registers that have reserved bits, read-modify-write operations must be used so that the reserved
bits are written with their previous values.
The USB host controller registers are listed in Table 1 .
Table 1. USB Host Controller Registers
Address Acronym Register Description Section
01E2 5000h HCREVISION OHCI Revision Number Register Section 3.1
01E2 5004h HCCONTROL HC Operating Mode Register Section 3.2
01E2 5008h HCCOMMANDSTATUS HC Command and Status Register Section 3.3
01E2 500Ch HCINTERRUPTSTATUS HC Interrupt and Status Register Section 3.4
01E2 5010h HCINTERRUPTENABLE HC Interrupt Enable Register Section 3.5
01E2 5014h HCINTERRUPTDISABLE HC Interrupt Disable Register Section 3.6
01E2 5018h HCHCCA HC HCAA Address Register
(1)
Section 3.7
01E2 501Ch HCPERIODCURRENTED HC Current Periodic Register
(1)
Section 3.8
01E2 5020h HCCONTROLHEADED HC Head Control Register
(1)
Section 3.9
01E2 5024h HCCONTROLCURRENTED HC Current Control Register
(1)
Section 3.10
01E2 5028h HCBULKHEADED HC Head Bulk Register
(1)
Section 3.11
01E2 502Ch HCBULKCURRENTED HC Current Bulk Register
(1)
Section 3.12
01E2 5030h HCDONEHEAD HC Head Done Register
(1)
Section 3.13
01E2 5034h HCFMINTERVAL HC Frame Interval Register Section 3.14
01E2 5038h HCFMREMAINING HC Frame Remaining Register Section 3.15
01E2 503Ch HCFMNUMBER HC Frame Number Register Section 3.16
01E2 5040h HCPERIODICSTART HC Periodic Start Register Section 3.17
01E2 5044h HCLSTHRESHOLD HC Low-Speed Threshold Register Section 3.18
01E2 5048h HCRHDESCRIPTORA HC Root Hub A Register Section 3.19
01E2 504Ch HCRHDESCRIPTORB HC Root Hub B Register Section 3.20
01E2 5050h HCRHSTATUS HC Root Hub Status Register Section 3.21
01E2 5054h HCRHPORTSTATUS1 HC Port 1 Status and Control Register
(2)
Section 3.22
01E2 5058h HCRHPORTSTATUS2 HC Port 2 Status and Control Register
(3)
Section 3.23
(1)
Restrictions apply to the physical addresses used in these registers (see Section 2.7 ).
(2)
Connected to the integrated USB1.1 phy pins (USB1_DM, USB1_DP).
(3)
Although the controller implements two ports, the second port cannot be used.
Universal Serial Bus OHCI Host Controller12 SPRUFM8 – September 2008
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