TMS320C674x/OMAP-L1x Processor Ethernet Media Access Controller (EMAC)/ Management Data Input/Output (MDIO) Module User's Guide Literature Number: SPRUFL5B April 2011
SPRUFL5B – April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated
Preface ...................................................................................................................................... 10 1 Introduction ...................................................................................................................... 12 2 3 ............................................................................................. 12 ................................................................................................................. 12 1.
www.ti.com (C0RXIMAX-C2RXIMAX) 3.13 4 4 68 EMAC Control Module Interrupt Core Transmit Interrupts Per Millisecond Registers (C0TXIMAX-C2TXIMAX) .............................................................................................. 69 ................................................................................................................. 70 ................................................................................ 70 4.2 MDIO Control Register (CONTROL) ...........................
www.ti.com ...................................................................... 114 5.32 FIFO Control Register (FIFOCONTROL) ......................................................................... 114 5.33 MAC Configuration Register (MACCONFIG) ..................................................................... 115 5.34 Soft Reset Register (SOFTRESET) ................................................................................ 115 5.35 MAC Source Address Low Bytes Register (MACSRCADDRLO) ........
www.ti.com List of Figures 1 EMAC and MDIO Block Diagram ........................................................................................ 13 2 Ethernet Configuration—MII Connections .............................................................................. 15 3 Ethernet Configuration—RMII Connections ............................................................................ 16 4 Ethernet Frame Format ......................................................................................
www.ti.com 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 ........................................................... 92 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) ..................................................... 93 MAC Input Vector Register (MACINVECTOR) ........................................................................ 94 MAC End Of Interrupt Vector Register (MACEOIVECTOR) .............................
www.ti.com List of Tables 1 EMAC and MDIO Signals for MII Interface............................................................................. 15 2 EMAC and MDIO Signals for RMII Interface........................................................................... 16 3 Ethernet Frame Description .............................................................................................. 17 4 Basic Descriptor Description .............................................................................
www.ti.com 46 Transmit Interrupt Mask Set Register (TXINTMASKSET) Field Descriptions ..................................... 92 47 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) Field Descriptions ............................... 93 48 MAC Input Vector Register (MACINVECTOR) Field Descriptions .................................................. 94 49 MAC End Of Interrupt Vector Register (MACEOIVECTOR) Field Descriptions...................................
Preface SPRUFL5B – April 2011 Read This First About This Manual This document provides a functional description of the Ethernet Media Access Controller (EMAC) and physical layer (PHY) device Management Data Input/Output (MDIO) module integrated in the device. Included are the features of the EMAC and MDIO modules, a discussion of their architecture and operation, how these modules connect to the outside world, and the registers description for each module.
www.ti.com Related Documentation From Texas Instruments SPRUGM7 — OMAP-L138 Applications Processor System Reference Guide. Describes the System-on-Chip (SoC) including the ARM subsystem, DSP subsystem, system memory, device clocking, phase-locked loop controller (PLLC), power and sleep controller (PSC), power management, ARM interrupt controller (AINTC), and system configuration module. SPRUFK9 — TMS320C674x/OMAP-L1x Processor Peripherals Overview Reference Guide.
User's Guide SPRUFL5B – April 2011 EMAC/MDIO Module 1 Introduction This document provides a functional description of the Ethernet Media Access Controller (EMAC) and physical layer (PHY) device Management Data Input/Output (MDIO) module integrated in the device. Included are the features of the EMAC and MDIO modules, a discussion of their architecture and operation, how these modules connect to the outside world, and a description of the registers for each module.
Introduction www.ti.com 1.3 Functional Block Diagram Figure 1 shows the three main functional modules of the EMAC/MDIO peripheral: • EMAC control module • EMAC module • MDIO module The EMAC control module is the main interface between the device core processor to the EMAC and MDIO modules. The EMAC control module controls device interrupts and incorporates an 8k-byte internal RAM to hold EMAC buffer descriptors (also known as CPPI RAM). The MDIO module implements the 802.
Architecture 1.4 www.ti.com Industry Standard(s) Compliance Statement The EMAC peripheral conforms to the IEEE 802.3 standard, describing the Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer specifications. The IEEE 802.3 standard has also been adopted by ISO/IEC and re-designated as ISO/IEC 8802-3:2000(E). However, the EMAC deviates from the standard in the way it handles transmit underflow errors.
Architecture www.ti.com The individual EMAC and MDIO signals for the MII interface are summarized in Table 1. For more information, refer to either the IEEE 802.3 standard or ISO/IEC 8802-3:2000(E). Figure 2. Ethernet Configuration—MII Connections MII_TXCLK MII_TXD[3−0] 2.5 MHz or 25 MHz MII_TXEN EMAC MII_COL System core MII_CRS MII_RXCLK MII_RXD[3−0] Physical layer device (PHY) Transformer MII_RXDV MDIO MII_RXER RJ−45 MDIO_CLK MDIO_D Table 1.
Architecture www.ti.com Table 1. EMAC and MDIO Signals for MII Interface (continued) 2.3.2 Signal Type Description MDIO_CLK O Management data clock (MDIO_CLK). The MDIO data clock is sourced by the MDIO module on the system. It is used to synchronize MDIO data access operations done on the MDIO pin. The frequency of this clock is controlled by the CLKDIV bits in the MDIO control register (CONTROL). MDIO_D I/O Management data input output (MDIO_D).
Architecture www.ti.com 2.4 Ethernet Protocol Overview A brief overview of the Ethernet protocol is given in the following subsections. See the IEEE 802.3 standard document for in-depth information on the Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method. 2.4.1 Ethernet Frame Format All the Ethernet technologies use the same frame structure. The format of an Ethernet frame is shown in Figure 4 and described in Table 3.
Architecture 2.4.2 www.ti.com Ethernet’s Multiple Access Protocol Nodes in an Ethernet Local Area Network are interconnected by a broadcast channel -- when an EMAC port transmits a frame, all the adapters on the local network receive the frame. Carrier Sense Multiple Access with Collision Detection (CSMA/CD) algorithms are used when the EMAC operates in half-duplex mode.
Architecture www.ti.com Table 4. Basic Descriptor Description Word Offset Field Field Description 0 Next Descriptor Pointer The next descriptor pointer is used to create a single linked list of descriptors. Each descriptor describes a packet or a packet fragment. When a descriptor points to a single buffer packet or the first fragment of a packet, the start of packet (SOP) flag is set in the flags field.
Architecture 2.5.2 www.ti.com Transmit and Receive Descriptor Queues The EMAC module processes descriptors in linked lists as discussed in Section 2.5.1. The lists used by the EMAC are maintained by the application software through the use of the head descriptor pointer registers (HDP). The EMAC supports eight channels for transmit and eight channels for receive.
Architecture www.ti.com 2.5.3 Transmit and Receive EMAC Interrupts The EMAC processes descriptors in linked list chains as discussed in Section 2.5.1, using the linked list queue mechanism discussed in Section 2.5.2. The EMAC synchronizes descriptor list processing through the use of interrupts to the software application. The interrupts are controlled by the application using the interrupt masks, global interrupt enable, and the completion pointer register (CP).
Architecture www.ti.com Figure 7. Transmit Buffer Descriptor Format Word 0 31 0 Next Descriptor Pointer Word 1 31 0 Buffer Pointer Word 2 31 16 15 Buffer Offset 0 Buffer Length Word 3 31 30 29 28 27 26 SOP EOP OWNER EOQ TDOWNCMPLT PASSCRC 25 15 16 Reserved 0 Packet Length Example 1. Transmit Buffer Descriptor in C Structure Format /* // EMAC Descriptor // // The following is the format of a single buffer descriptor // on the EMAC.
Architecture www.ti.com 2.5.4.1 Next Descriptor Pointer The next descriptor pointer points to the 32-bit word aligned memory address of the next buffer descriptor in the transmit queue. This pointer is used to create a linked list of buffer descriptors. If the value of this pointer is zero, then the current buffer is the last buffer in the queue. The software application must set this value prior to adding the descriptor to the active transmit list. This pointer is not altered by the EMAC.
Architecture 2.5.4.7 www.ti.com End of Packet (EOP) Flag When set, this flag indicates that the descriptor points to a packet buffer that is last for a given packet. In the case of a single fragment packet, both the start of packet (SOP) and EOP flags are set. Otherwise, the descriptor pointing to the last packet buffer for the packet sets the EOP flag. This bit is set by the software application and is not altered by the EMAC. 2.5.4.
Architecture www.ti.com 2.5.5 Receive Buffer Descriptor Format A receive (RX) buffer descriptor (Figure 8) is a contiguous block of four 32-bit data words aligned on a 32-bit boundary that describes a packet or a packet fragment. Example 2 shows the receive buffer descriptor described by a C structure. 2.5.5.1 Next Descriptor Pointer This pointer points to the 32–bit word aligned memory address of the next buffer descriptor in the receive queue.
Architecture www.ti.com Example 2. Receive Buffer Descriptor in C Structure Format /* // EMAC Descriptor // // The following is the format of a single buffer descriptor // on the EMAC.
Architecture www.ti.com 2.5.5.4 Buffer Length This 16-bit field is used for two purposes: • Before the descriptor is first placed on the receive queue by the application software, the buffer length field is first initialized by the software to have the physical size of the empty data buffer pointed to by the buffer pointer field.
Architecture 2.5.5.11 www.ti.com Pass CRC (PASSCRC) Flag This flag is set by the EMAC in the SOP buffer descriptor if the received packet includes the 4-byte CRC. This flag should be cleared by the software application before submitting the descriptor to the receive queue. 2.5.5.12 Jabber Flag This flag is set by the EMAC in the SOP buffer descriptor, if the received packet is a jabber frame and was not discarded because the RXCEFEN bit was set in the RXMBPENABLE.
Architecture www.ti.com 2.6 EMAC Control Module The EMAC control module (Figure 9) interfaces the EMAC and MDIO modules to the rest of the system, and also provides a local memory space to hold EMAC packet buffer descriptors. Local memory is used to help avoid contention with device memory spaces. Other functions include the bus arbiter, and interrupt logic control. Figure 9.
Architecture 2.6.3 www.ti.com Interrupt Control Interrupt conditions generated by the EMAC and MDIO modules are combined into four interrupt signals that are routed to three independent interrupt cores in the EMAC control module; the interrupt cores then relay the interrupt signals to the CPU interrupt controller.
Architecture www.ti.com Figure 10. MDIO Module Block Diagram Peripheral clock EMAC control module MDIO clock generator USERINT PHY monitoring LINKINT Configuration bus 2.7.1.1 MDIO interface MDCLK MDIO PHY polling Control registers and logic MDIO Clock Generator The MDIO clock generator controls the MDIO clock based on a divide-down of the peripheral clock in the EMAC control module. The MDIO clock is specified to run up to 2.5 MHz, although typical operation would be 1.0 MHz.
Architecture 2.7.2 www.ti.com MDIO Module Operational Overview The MDIO module implements the 802.3 serial management interface to interrogate and control an Ethernet PHY, using a shared two-wired bus. It separately performs autodetection and records the current link status of up to 32 PHYs, polling all 32 MDIO addresses.
Architecture www.ti.com 2.7.2.1 Initializing the MDIO Module The following steps are performed by the application software or device driver to initialize the MDIO device: 1. Configure the PREAMBLE and CLKDIV bits in the MDIO control register (CONTROL). 2. Enable the MDIO module by setting the ENABLE bit in CONTROL. 3.
Architecture 2.7.2.4 www.ti.com Example of MDIO Register Access Code The MDIO module uses the MDIO user access register (USERACCESSn) to access the PHY control registers.
Architecture www.ti.com 2.8 EMAC Module This section discusses the architecture and basic function of the EMAC module. 2.8.1 EMAC Module Components The EMAC module (Figure 11) interfaces to the outside world through the Media Independent Interface (MII) and/or Reduced Media Independent Interface (RMII). The interface between the EMAC module and the system core is provided through the EMAC control module.
Architecture 2.8.1.4 www.ti.com Transmit DMA Engine The transmit DMA engine is the interface between the transmit FIFO and the CPU. It interfaces to the CPU through the bus arbiter in the EMAC control module. 2.8.1.5 Transmit FIFO The transmit FIFO consists of three cells of 64-bytes each and associated control logic. The FIFO buffers data in preparation for transmission. 2.8.1.
Architecture www.ti.com The EMAC module operates independently of the CPU. It is configured and controlled by its register set mapped into device memory. Information about data packets is communicated by use of 16-byte descriptors that are placed in an 8K-byte block of RAM in the EMAC control module (CPPI buffer descriptor memory). For transmit operations, each 16-byte descriptor describes a packet or packet fragment in the system's internal or external memory.
Architecture www.ti.com In either case, receive flow control prevents frame reception by issuing the flow control appropriate for the current mode of operation. Receive flow control prevents reception of frames on the EMAC until all of the triggering conditions clear, at which time frames may again be received by the EMAC. Receive flow control is enabled by the RXBUFFERFLOWEN bit in the MAC control register (MACCONTROL). The EMAC is configured for collision or IEEE 802.
Architecture www.ti.com 2.9.2 Data Transmission The EMAC passes data to the PHY from the transmit FIFO (when enabled). Data is synchronized to the transmit clock rate. Transmission begins when there are TXCELLTHRESH cells of 64 bytes each, or a complete packet, in the FIFO. 2.9.2.1 Transmit Control A jam sequence is output if a collision is detected on a transmit packet. If the collision was late (after the first 64 bytes have been transmitted), the collision is ignored.
Architecture 2.9.2.6 www.ti.com Transmit Flow Control Incoming pause frames are acted upon, when enabled, to prevent the EMAC from transmitting any further frames. Incoming pause frames are only acted upon when the FULLDUPLEX and TXFLOWEN bits in the MAC control register (MACCONTROL) are set. Pause frames are not acted upon in half-duplex mode. Pause frame action is taken if enabled, but normally the frame is filtered and not transferred to memory.
Architecture www.ti.com 2.10 Packet Receive Operation 2.10.1 Receive DMA Host Configuration To • • • • • • • • • • 2.10.2 configure the receive DMA for operation the host must: Initialize the receive addresses. Initialize the receive channel n DMA head descriptor pointer registers (RXnHDP) to 0. Write the MAC address hash n registers (MACHASH1 and MACHASH2), if multicast addressing is desired.
Architecture 2.10.4 www.ti.com Hardware Receive QOS Support Hardware receive quality of service (QOS) is supported, when enabled, by the Tag Protocol Identifier format and the associated Tag Control Information (TCI) format priority field. When the incoming frame length/type value is equal to 81.00h, the EMAC recognizes the frame as an Ethernet Encoded Tag Protocol Type. The two octets immediately following the protocol type contain the 16-bit TCI field.
Architecture www.ti.com 2.10.7 Receive Frame Classification Received frames are proper (good) frames, if they are between 64 bytes and the value in the receive maximum length register (RXMAXLEN) bytes in length (inclusive) and contain no code, align, or CRC errors. Received frames are long frames, if their frame count exceeds the value in RXMAXLEN. The RXMAXLEN reset (default) value is 5EEh (1518 in decimal). Long received frames are either oversized or jabber frames.
Architecture www.ti.com Table 5. Receive Frame Treatment Summary 44 Address Match RXCAFEN RXCEFEN RXCMFEN RXCSFEN 0 0 X X X No frames transferred. 0 1 0 0 0 Proper frames transferred to promiscuous channel. 0 1 0 0 1 Proper/undersized data frames transferred to promiscuous channel. 0 1 0 1 0 Proper data and control frames transferred to promiscuous channel. 0 1 0 1 1 Proper/undersized data and control frames transferred to promiscuous channel.
Architecture www.ti.com 2.10.
Architecture www.ti.com 2.11 Packet Transmit Operation The transmit DMA is an eight channel interface. Priority between the eight queues may be either fixed or round-robin as selected by the TXPTYPE bit in the MAC control register (MACCONTROL). If the priority type is fixed, then channel 7 has the highest priority and channel 0 has the lowest priority. Round-robin priority proceeds from channel 0 to channel 7. 2.11.
Architecture www.ti.com 2.12 Receive and Transmit Latency The transmit and receive FIFOs each contain three 64-byte cells. The EMAC begins transmission of a packet on the wire after TXCELLTHRESH (configurable through the FIFO control register) cells, or a complete packet, are available in the FIFO. Transmit underrun cannot occur for packet sizes of TXCELLTHRESH times 64 bytes (or less).
Architecture www.ti.com 2.14 Reset Considerations 2.14.1 Software Reset Considerations Peripheral clock and reset control is done through the Power and Sleep Controller (PSC) module included with the device. For more on how the EMAC, MDIO, and EMAC control module are disabled or placed in reset at runtime from the registers located in the PSC module, see Section 2.17. With the EMAC still in reset (PSC in the default state): 1.
Architecture www.ti.com 2.15 Initialization 2.15.1 Enabling the EMAC/MDIO Peripheral When the device is powered on, the EMAC peripheral may be in a disabled state. Before any EMAC specific initialization can take place, the EMAC needs to be enabled; otherwise, its registers cannot be written and the reads will all return a value of zero. The EMAC/MDIO is enabled through the Power and Sleep Controller (PSC) registers.
Architecture 2.15.4 www.ti.com EMAC Module Initialization The EMAC module is used to send and receive data packets over the network. This is done by maintaining up to eight transmit and receive descriptor queues. The EMAC module configuration must also be kept up-to-date based on PHY negotiation results returned from the MDIO module. Most of the work in developing an application or device driver for Ethernet is programming this module.
Architecture www.ti.com 2.16 Interrupt Support 2.16.
Architecture www.ti.com When the EMAC completes a packet reception, the EMAC issues an interrupt to the CPU by writing the packet's last buffer descriptor address to the appropriate channel queue's receive completion pointer located in the state RAM block. The interrupt is generated by the write when enabled by the interrupt mask, regardless of the value written.
Architecture www.ti.com The receive host error conditions are: • Ownership bit not set in input buffer • Zero buffer pointer The application software must acknowledge the EMAC control module after receiving host error interrupts by writing the appropriate CnMISC key to the EMAC End-Of-Interrupt Vector (MACEOIVECTOR). See Section 5.12 for the acknowledge key values. 2.16.1.5 Receive Threshold Interrupts Each of the eight receive channels have a corresponding receive threshold interrupt (RXnTHRESHPEND).
Architecture 2.16.2.2 www.ti.com User Access Completion Interrupt When the GO bit in one of the MDIO register USERACCESS0 transitions from 1 to 0 (indicating completion of a user access) and the corresponding USERINTMASKSET bit in the MDIO user command complete interrupt mask set register (USERINTMASKSET) corresponding to USERACCESS0 is set, a user access completion interrupt (USERINT) is asserted.
Architecture www.ti.com 2.17 Power Management Each of the three main components of the EMAC peripheral can independently be placed in reduced-power modes to conserve power during periods of low activity. The power management of the EMAC peripheral is controlled by the processor Power and Sleep Controller (PSC). The PSC acts as a master controller for power management on behalf of all of the peripherals on the device.
EMAC Control Module Registers 3 www.ti.com EMAC Control Module Registers Table 8 lists the memory-mapped registers for the EMAC control module. See your device-specific data manual for the memory address of these registers. Table 8. EMAC Control Module Registers Offset 56 Acronym Register Description 0h REVID EMAC Control Module Revision ID Register Section 3.1 Section 4h SOFTRESET EMAC Control Module Software Reset Register Section 3.
EMAC Control Module Registers www.ti.com Table 8. EMAC Control Module Registers (continued) Offset 3.1 Acronym Register Description 70h C0RXIMAX EMAC Control Module Interrupt Core 0 Receive Interrupts Per Millisecond Register Section 3.12 Section 74h C0TXIMAX EMAC Control Module Interrupt Core 0 Transmit Interrupts Per Millisecond Register Section 3.13 78h C1RXIMAX EMAC Control Module Interrupt Core 1 Receive Interrupts Per Millisecond Register Section 3.
EMAC Control Module Registers 3.2 www.ti.com EMAC Control Module Software Reset Register (SOFTRESET) The EMAC Control Module Software Reset Register (SOFTRESET) is shown in Figure 13 and described in Table 10. Figure 13. EMAC Control Module Software Reset Register (SOFTRESET) 31 16 Reserved R-0 15 1 0 Reserved RESET R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 10.
EMAC Control Module Registers www.ti.com 3.3 EMAC Control Module Interrupt Control Register (INTCONTROL) The EMAC control module interrupt control register (INTCONTROL) is shown in Figure 14 and described in Table 11 . The settings in the INTCONTROL register are used in conjunction with the CnRXIMAX and CnTXIMAX registers. Figure 14.
EMAC Control Module Registers 3.4 www.ti.com EMAC Control Module Interrupt Core Receive Threshold Interrupt Enable Registers (C0RXTHRESHEN-C2RXTHRESHEN) The EMAC control module interrupt core 0-2 receive threshold interrupt enable register (CnRXTHRESHEN) is shown in Figure 15 and described in Table 12. Figure 15.
EMAC Control Module Registers www.ti.com 3.5 EMAC Control Module Interrupt Core Receive Interrupt Enable Registers (C0RXEN-C2RXEN) The EMAC control module interrupt core 0-2 receive interrupt enable register (CnRXEN) is shown in Figure 16 and described in Table 13 Figure 16.
EMAC Control Module Registers 3.6 www.ti.com EMAC Control Module Interrupt Core Transmit Interrupt Enable Registers (C0TXEN-C2TXEN) The EMAC control module interrupt core 0-2 transmit interrupt enable register (CnTXEN) is shown in Figure 17 and described in Table 14 Figure 17.
EMAC Control Module Registers www.ti.com 3.7 EMAC Control Module Interrupt Core Miscellaneous Interrupt Enable Registers (C0MISCEN-C2MISCEN) The EMAC control module interrupt core 0-2 miscellaneous interrupt enable register (CnMISCEN) is shown in Figure 18 and described in Table 15 Figure 18.
EMAC Control Module Registers 3.8 www.ti.com EMAC Control Module Interrupt Core Receive Threshold Interrupt Status Registers (C0RXTHRESHSTAT-C2RXTHRESHSTAT) The EMAC control module interrupt core 0-2 receive threshold interrupt status register (CnRXTHRESHSTAT) is shown in Figure 19 and described in Table 16 Figure 19.
EMAC Control Module Registers www.ti.com 3.9 EMAC Control Module Interrupt Core Receive Interrupt Status Registers (C0RXSTAT-C2RXSTAT) The EMAC control module interrupt core 0-2 receive interrupt status register (CnRXSTAT) is shown in Figure 20 and described in Table 17 Figure 20.
EMAC Control Module Registers www.ti.com 3.10 EMAC Control Module Interrupt Core Transmit Interrupt Status Registers (C0TXSTAT-C2TXSTAT) The EMAC control module interrupt core 0-2 transmit interrupt status register (CnTXSTAT) is shown in Figure 21 and described in Table 18 Figure 21.
EMAC Control Module Registers www.ti.com 3.11 EMAC Control Module Interrupt Core Miscellaneous Interrupt Status Registers (C0MISCSTAT-C2MISCSTAT) The EMAC control module interrupt core 0-2 miscellaneous interrupt status register (CnMISCSTAT) is shown in Figure 22 and described in Table 19 Figure 22.
EMAC Control Module Registers www.ti.com 3.12 EMAC Control Module Interrupt Core Receive Interrupts Per Millisecond Registers (C0RXIMAX-C2RXIMAX) The EMAC control module interrupt core 0-2 receive interrupts per millisecond register (CnRXIMAX) is shown in Figure 23 and described in Table 20 Figure 23.
EMAC Control Module Registers www.ti.com 3.13 EMAC Control Module Interrupt Core Transmit Interrupts Per Millisecond Registers (C0TXIMAX-C2TXIMAX) The EMAC control module interrupt core 0-2 transmit interrupts per millisecond register (CnTXIMAX) is shown in Figure 24 and described in Table 21 Figure 24.
MDIO Registers 4 www.ti.com MDIO Registers Table 22 lists the memory-mapped registers for the MDIO module. See your device-specific data manual for the memory address of these registers. Table 22. Management Data Input/Output (MDIO) Registers Offset 4.1 Acronym Register Description 0h REVID MDIO Revision ID Register Section 4.1 Section 4h CONTROL MDIO Control Register Section 4.2 8h ALIVE PHY Alive Status register Section 4.3 Ch LINK PHY Link Status Register Section 4.
MDIO Registers www.ti.com 4.2 MDIO Control Register (CONTROL) The MDIO control register (CONTROL) is shown in Figure 26 and described in Table 24. Figure 26.
MDIO Registers 4.3 www.ti.com PHY Acknowledge Status Register (ALIVE) The PHY acknowledge status register (ALIVE) is shown in Figure 27 and described in Table 25. Figure 27. PHY Acknowledge Status Register (ALIVE) 31 0 ALIVE R/W1C-0 LEGEND: R/W = Read/Write; W1C = Write 1 to clear (writing a 0 has no effect); -n = value after reset Table 25. PHY Acknowledge Status Register (ALIVE) Field Descriptions Bit Field 31-0 ALIVE 4.4 Value Description MDIO Alive bits.
MDIO Registers www.ti.com 4.5 MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) The MDIO link status change interrupt (unmasked) register (LINKINTRAW) is shown in Figure 29 and described in Table 27. Figure 29. MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) 31 16 Reserved R-0 15 1 0 Reserved 2 USERPHY1 USERPHY0 R-0 R/W1C-0 R/W1C-0 LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear (writing a 0 has no effect); -n = value after reset Table 27.
MDIO Registers 4.6 www.ti.com MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) The MDIO link status change interrupt (masked) register (LINKINTMASKED) is shown in Figure 30 and described in Table 28. Figure 30.
MDIO Registers www.ti.com 4.7 MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) The MDIO user command complete interrupt (unmasked) register (USERINTRAW) is shown in Figure 31 and described in Table 29. Figure 31.
MDIO Registers 4.8 www.ti.com MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) The MDIO user command complete interrupt (masked) register (USERINTMASKED) is shown in Figure 32 and described in Table 30. Figure 32.
MDIO Registers www.ti.com 4.9 MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) The MDIO user command complete interrupt mask set register (USERINTMASKSET) is shown in Figure 33 and described in Table 31. Figure 33.
MDIO Registers www.ti.com 4.10 MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) The MDIO user command complete interrupt mask clear register (USERINTMASKCLEAR) is shown in Figure 34 and described in Table 32. Figure 34.
MDIO Registers www.ti.com 4.11 MDIO User Access Register 0 (USERACCESS0) The MDIO user access register 0 (USERACCESS0) is shown in Figure 35 and described in Table 33. Figure 35. MDIO User Access Register 0 (USERACCESS0) 31 30 29 28 GO WRITE ACK Reserved 26 25 REGADR 21 20 PHYADR 16 R/W1S-0 R/W-0 R/W-0 R-0 R/W-0 R/W-0 15 0 DATA R/W-0 LEGEND: R/W = Read/Write; R = Read only; W1S = Write 1 to set (writing a 0 has no effect); -n = value after reset Table 33.
MDIO Registers www.ti.com 4.12 MDIO User PHY Select Register 0 (USERPHYSEL0) The MDIO user PHY select register 0 (USERPHYSEL0) is shown in Figure 36 and described in Table 34. Figure 36. MDIO User PHY Select Register 0 (USERPHYSEL0) 31 16 Reserved R-0 15 7 6 5 Reserved 8 LINKSEL LINKINTENB Rsvd 4 PHYADRMON 0 R-0 R/W-0 R/W-0 R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 34.
MDIO Registers www.ti.com 4.13 MDIO User Access Register 1 (USERACCESS1) The MDIO user access register 1 (USERACCESS1) is shown in Figure 37 and described in Table 35. Figure 37. MDIO User Access Register 1 (USERACCESS1) 31 30 29 28 GO WRITE ACK Reserved 26 25 REGADR 21 20 PHYADR 16 R/W1S-0 R/W-0 R/W-0 R-0 R/W-0 R/W-0 15 0 DATA R/W-0 LEGEND: R/W = Read/Write; R = Read only; W1S = Write 1 to set (writing a 0 has no effect); -n = value after reset Table 35.
MDIO Registers www.ti.com 4.14 MDIO User PHY Select Register 1 (USERPHYSEL1) The MDIO user PHY select register 1 (USERPHYSEL1) is shown in Figure 38 and described in Table 36. Figure 38. MDIO User PHY Select Register 1 (USERPHYSEL1) 31 16 Reserved R-0 15 7 6 5 Reserved 8 LINKSEL LINKINTENB Rsvd 4 PHYADRMON 0 R-0 R/W-0 R/W-0 R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 36.
EMAC Module Registers www.ti.com 5 EMAC Module Registers Table 37 lists the memory-mapped registers for the EMAC. See your device-specific data manual for the memory address of these registers. Table 37. Ethernet Media Access Controller (EMAC) Registers Offset Acronym Register Description 0h TXREVID Transmit Revision ID Register Section 5.1 Section 4h TXCONTROL Transmit Control Register Section 5.2 8h TXTEARDOWN Transmit Teardown Register Section 5.
EMAC Module Registers www.ti.com Table 37. Ethernet Media Access Controller (EMAC) Registers (continued) Offset 84 Acronym Register Description Section 164h MACSTATUS MAC Status Register Section 5.30 168h EMCONTROL Emulation Control Register Section 5.31 16Ch FIFOCONTROL FIFO Control Register Section 5.32 170h MACCONFIG MAC Configuration Register Section 5.33 174h SOFTRESET Soft Reset Register Section 5.34 1D0h MACSRCADDRLO MAC Source Address Low Bytes Register Section 5.
EMAC Module Registers www.ti.com Table 37. Ethernet Media Access Controller (EMAC) Registers (continued) Offset Acronym Register Description 67Ch RX7CP Receive Channel 7 Completion Pointer Register Section 200h RXGOODFRAMES Good Receive Frames Register Section 5.50.1 204h RXBCASTFRAMES Broadcast Receive Frames Register Section 5.50.2 208h RXMCASTFRAMES Multicast Receive Frames Register Section 5.50.3 20Ch RXPAUSEFRAMES Pause Receive Frames Register Section 5.50.
EMAC Module Registers 5.1 www.ti.com Transmit Revision ID Register (TXREVID) The transmit revision ID register (TXREVID) is shown in Figure 39 and described in Table 38. Figure 39. Transmit Revision ID Register (TXREVID) 31 0 TXREV R-4EC0 020Dh LEGEND: R = Read only; -n = value after reset Table 38. Transmit Revision ID Register (TXREVID) Field Descriptions Bit 31-0 Field Value TXREV Transmit module revision 4EC0 020Dh 5.
EMAC Module Registers www.ti.com 5.3 Transmit Teardown Register (TXTEARDOWN) The transmit teardown register (TXTEARDOWN) is shown in Figure 41 and described in Table 40. Figure 41. Transmit Teardown Register (TXTEARDOWN) 31 16 Reserved R-0 15 3 2 0 Reserved TXTDNCH R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 40.
EMAC Module Registers 5.4 www.ti.com Receive Revision ID Register (RXREVID) The receive revision ID register (RXREVID) is shown in Figure 42 and described in Table 41. Figure 42. Receive Revision ID Register (RXREVID) 31 0 RXREV R-4EC0 020Dh LEGEND: R = Read only; -n = value after reset Table 41. Receive Revision ID Register (RXREVID) Field Descriptions Bit 31-0 Field Value RXREV Receive module revision 4EC0 020Dh 5.
EMAC Module Registers www.ti.com 5.6 Receive Teardown Register (RXTEARDOWN) The receive teardown register (RXTEARDOWN) is shown in Figure 44 and described in Table 43. Figure 44. Receive Teardown Register (RXTEARDOWN) 31 16 Reserved R-0 15 3 2 0 Reserved RXTDNCH R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 43.
EMAC Module Registers 5.7 www.ti.com Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) The transmit interrupt status (unmasked) register (TXINTSTATRAW) is shown in Figure 45 and described in Table 44. Figure 45.
EMAC Module Registers www.ti.com 5.8 Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) The transmit interrupt status (masked) register (TXINTSTATMASKED) is shown in Figure 46 and described in Table 45. Figure 46.
EMAC Module Registers 5.9 www.ti.com Transmit Interrupt Mask Set Register (TXINTMASKSET) The transmit interrupt mask set register (TXINTMASKSET) is shown in Figure 47 and described in Table 46. Figure 47.
EMAC Module Registers www.ti.com 5.10 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) The transmit interrupt mask clear register (TXINTMASKCLEAR) is shown in Figure 48 and described in Table 47. Figure 48.
EMAC Module Registers www.ti.com 5.11 MAC Input Vector Register (MACINVECTOR) The MAC input vector register (MACINVECTOR) is shown in Figure 49 and described in Table 48. Figure 49. MAC Input Vector Register (MACINVECTOR) 31 28 27 26 25 24 Reserved STATPEND HOSTPEND LINKINT0 USERINT0 R-0 R-0 R-0 R-0 R-0 15 8 23 16 TXPEND R-0 7 0 RXTHRESHPEND RXPEND R-0 R-0 LEGEND: R = Read only; -n = value after reset Table 48.
EMAC Module Registers www.ti.com 5.12 MAC End Of Interrupt Vector Register (MACEOIVECTOR) The MAC end of interrupt vector register (MACEOIVECTOR) is shown in Figure 50 and described in Table 49. Figure 50. MAC End Of Interrupt Vector Register (MACEOIVECTOR) 31 16 Reserved R-0 15 5 4 0 Reserved INTVECT R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 49.
EMAC Module Registers www.ti.com 5.13 Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) The receive interrupt status (unmasked) register (RXINTSTATRAW) is shown in Figure 51 and described in Table 50. Figure 51.
EMAC Module Registers www.ti.com 5.14 Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) The receive interrupt status (masked) register (RXINTSTATMASKED) is shown in Figure 52 and described in Table 51. Figure 52.
EMAC Module Registers www.ti.com 5.15 Receive Interrupt Mask Set Register (RXINTMASKSET) The receive interrupt mask set register (RXINTMASKSET) is shown in Figure 53 and described in Table 52. Figure 53.
EMAC Module Registers www.ti.com 5.16 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) The receive interrupt mask clear register (RXINTMASKCLEAR) is shown in Figure 54 and described in Table 53. Figure 54.
EMAC Module Registers www.ti.com 5.17 MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) The MAC interrupt status (unmasked) register (MACINTSTATRAW) is shown in Figure 55 and described in Table 54. Figure 55. MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) 31 16 Reserved R-0 15 1 0 Reserved 2 HOSTPEND STATPEND R-0 R-0 R-0 LEGEND: R = Read only; -n = value after reset Table 54.
EMAC Module Registers www.ti.com 5.19 MAC Interrupt Mask Set Register (MACINTMASKSET) The MAC interrupt mask set register (MACINTMASKSET) is shown in Figure 57 and described in Table 56. Figure 57. MAC Interrupt Mask Set Register (MACINTMASKSET) 31 16 Reserved R-0 15 1 0 Reserved 2 HOSTMASK STATMASK R-0 R/W1S-0 R/W1S-0 LEGEND: R/W = Read/Write; R = Read only; W1S = Write 1 to set (writing a 0 has no effect); -n = value after reset Table 56.
EMAC Module Registers www.ti.com 5.21 Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) The receive multicast/broadcast/promiscuous channel enable register (RXMBPENABLE) is shown in Figure 59 and described in Table 58. Figure 59.
EMAC Module Registers www.ti.com Table 58. Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) Field Descriptions (continued) Bit Field 22 RXCEFEN 21 Reserved 18-16 RXPROMCH 13 Reserved RXBROADCH 5 4-3 Frames containing errors are filtered. 1 Frames containing errors are transferred to memory. 0 Frames that do not address match are filtered. 1 Frames that do not address match are transferred to the promiscuous channel selected by RXPROMCH bits.
EMAC Module Registers www.ti.com Table 58.
EMAC Module Registers www.ti.com 5.22 Receive Unicast Enable Set Register (RXUNICASTSET) The receive unicast enable set register (RXUNICASTSET) is shown in Figure 60 and described in Table 59. Figure 60.
EMAC Module Registers www.ti.com 5.23 Receive Unicast Clear Register (RXUNICASTCLEAR) The receive unicast clear register (RXUNICASTCLEAR) is shown in Figure 61 and described in Table 60. Figure 61.
EMAC Module Registers www.ti.com 5.24 Receive Maximum Length Register (RXMAXLEN) The receive maximum length register (RXMAXLEN) is shown in Figure 62 and described in Table 61. Figure 62. Receive Maximum Length Register (RXMAXLEN) 31 16 Reserved R-0 15 0 RXMAXLEN R/W-5EEh LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 61.
EMAC Module Registers www.ti.com 5.26 Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) The receive filter low priority frame threshold register (RXFILTERLOWTHRESH) is shown in Figure 64 and described in Table 63. Figure 64. Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) 31 16 Reserved R-0 15 8 7 0 Reserved RXFILTERTHRESH R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 63.
EMAC Module Registers www.ti.com 5.28 Receive Channel Free Buffer Count Registers (RX0FREEBUFFER-RX7FREEBUFFER) The receive channel 0-7 free buffer count register (RXnFREEBUFFER) is shown in Figure 66 and described in Table 65. Figure 66. Receive Channel n Free Buffer Count Register (RXnFREEBUFFER) 31 16 Reserved R-0 15 0 RXnFREEBUF WI-0 LEGEND: R = Read only; WI = Write to increment; -n = value after reset Table 65.
EMAC Module Registers www.ti.com 5.29 MAC Control Register (MACCONTROL) The MAC control register (MACCONTROL) is shown in Figure 67 and described in Table 66. Figure 67.
EMAC Module Registers www.ti.com Table 66. MAC Control Register (MACCONTROL) Field Descriptions (continued) Bit 4 3 Field Reserved 1 LOOPBACK Description Transmit flow control enable bit. This bit determines if incoming pause frames are acted upon in full-duplex mode. Incoming pause frames are not acted upon in half-duplex mode, regardless of this bit setting. The RXMBPENABLE bits determine whether or not received pause frames are transferred to memory. 0 Transmit flow control is disabled.
EMAC Module Registers www.ti.com 5.30 MAC Status Register (MACSTATUS) The MAC status register (MACSTATUS) is shown in Figure 68 and described in Table 67. Figure 68. MAC Status Register (MACSTATUS) 31 30 24 23 20 19 18 16 IDLE Reserved TXERRCODE Rsvd TXERRCH R-0 R-0 R-0 R-0 R-0 15 12 11 10 8 RXERRCODE Reserved RXERRCH R-0 R-0 R-0 7 2 1 0 Reserved 3 RXQOSACT RXFLOWACT TXFLOWACT R-0 R-0 R-0 R-0 LEGEND: R = Read only; -n = value after reset Table 67.
EMAC Module Registers www.ti.com Table 67. MAC Status Register (MACSTATUS) Field Descriptions (continued) Bit 15-12 11 10-8 7-3 2 1 0 Field RXERRCODE Value 0-Fh Receive host error code. These bits indicate that EMAC detected receive DMA related host errors. The host should read this field after a host error interrupt (HOSTPEND) to determine the error. Host error interrupts require hardware reset in order to recover.
EMAC Module Registers www.ti.com 5.31 Emulation Control Register (EMCONTROL) The emulation control register (EMCONTROL) is shown in Figure 69 and described in Table 68. Figure 69. Emulation Control Register (EMCONTROL) 31 16 Reserved R-0 15 1 0 Reserved 2 SOFT FREE R-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 68.
EMAC Module Registers www.ti.com 5.33 MAC Configuration Register (MACCONFIG) The MAC configuration register (MACCONFIG) is shown in Figure 71 and described in Table 70. Figure 71. MAC Configuration Register (MACCONFIG) 31 24 23 16 TXCELLDEPTH RXCELLDEPTH R-3h R-3h 15 8 7 0 ADDRESSTYPE MACCFIG R-2h R-2h LEGEND: R = Read only; -n = value after reset Table 70.
EMAC Module Registers www.ti.com 5.35 MAC Source Address Low Bytes Register (MACSRCADDRLO) The MAC source address low bytes register (MACSRCADDRLO) is shown in Figure 73 and described in Table 72. Figure 73. MAC Source Address Low Bytes Register (MACSRCADDRLO) 31 16 Reserved R-0 15 8 7 0 MACSRCADDR0 MACSRCADDR1 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 72.
EMAC Module Registers www.ti.com 5.37 MAC Hash Address Register 1 (MACHASH1) The MAC hash registers allow group addressed frames to be accepted on the basis of a hash function of the address.
EMAC Module Registers www.ti.com 5.39 Back Off Test Register (BOFFTEST) The back off test register (BOFFTEST) is shown in Figure 77 and described in Table 76. Figure 77. Back Off Random Number Generator Test Register (BOFFTEST) 31 26 25 16 Reserved RNDNUM R-0 R-0 15 12 11 10 9 0 COLLCOUNT Reserved TXBACKOFF R-0 R-0 R-0 LEGEND: R = Read only; -n = value after reset Table 76.
EMAC Module Registers www.ti.com 5.41 Receive Pause Timer Register (RXPAUSE) The receive pause timer register (RXPAUSE) is shown in Figure 79 and described in Table 78. Figure 79. Receive Pause Timer Register (RXPAUSE) 31 16 Reserved R-0 15 0 PAUSETIMER R-0 LEGEND: R = Read only; -n = value after reset Table 78. Receive Pause Timer Register (RXPAUSE) Field Descriptions Bit Field 31-16 Reserved 15-0 PAUSETIMER Value 0 0-FFh Description Reserved Receive pause timer value.
EMAC Module Registers www.ti.com 5.43 MAC Address Low Bytes Register (MACADDRLO) The MAC address low bytes register used in address matching (MACADDRLO), is shown in Figure 81 and described in Table 80. Figure 81. MAC Address Low Bytes Register (MACADDRLO) 31 20 19 Reserved 21 VALID MATCHFILT CHANNEL R-0 R/W-x R/W-x R/W-x 15 8 18 16 7 0 MACADDR0 MACADDR1 R/W-x R/W-x LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; -x = value is indeterminate after reset Table 80.
EMAC Module Registers www.ti.com 5.44 MAC Address High Bytes Register (MACADDRHI) The MAC address high bytes register (MACADDRHI) is shown in Figure 82 and described in Table 81. Figure 82. MAC Address High Bytes Register (MACADDRHI) 31 24 23 16 MACADDR2 MACADDR3 R/W-x R/W-x 15 8 7 0 MACADDR4 MACADDR5 R/W-x R/W-x LEGEND: R/W = Read/Write; -x = value is indeterminate after reset Table 81.
EMAC Module Registers www.ti.com 5.46 Transmit Channel DMA Head Descriptor Pointer Registers (TX0HDP-TX7HDP) The transmit channel 0-7 DMA head descriptor pointer register (TXnHDP) is shown in Figure 84 and described in Table 83. Figure 84. Transmit Channel n DMA Head Descriptor Pointer Register (TXnHDP) 31 0 TXnHDP R/W-x LEGEND: R/W = Read/Write; -n = value after reset; -x = value is indeterminate after reset Table 83.
EMAC Module Registers www.ti.com 5.48 Transmit Channel Completion Pointer Registers (TX0CP-TX7CP) The transmit channel 0-7 completion pointer register (TXnCP) is shown in Figure 86 and described in Table 85. Figure 86. Transmit Channel n Completion Pointer Register (TXnCP) 31 0 TXnCP R/W-x LEGEND: R/W = Read/Write; -n = value after reset; -x = value is indeterminate after reset Table 85.
EMAC Module Registers www.ti.com 5.50 Network Statistics Registers The EMAC has a set of statistics that record events associated with frame traffic. The statistics values are cleared to zero 38 clocks after the rising edge of reset. When the GMIIEN bit in the MACCONTROL register is set, all statistics registers (see Figure 88) are write-to-decrement. The value written is subtracted from the register value with the result stored in the register.
EMAC Module Registers www.ti.com 5.50.4 Pause Receive Frames Register (RXPAUSEFRAMES) The total number of IEEE 802.3X pause frames received by the EMAC (whether acted upon or not). A pause frame is defined as having all of the following: • Contained any unicast, broadcast, or multicast address • Contained the length/type field value 88.
EMAC Module Registers 5.50.7 www.ti.com Receive Oversized Frames Register (RXOVERSIZED) The total number of oversized frames received on the EMAC. An oversized frame is defined as having all of the following: • Was any data or MAC control frame that matched a unicast, broadcast, or multicast address, or matched due to promiscuous mode • Was greater than RXMAXLEN in bytes • Had no CRC error, alignment error, or code error See Section 2.5.5 for definitions of alignment, code, and CRC errors.
EMAC Module Registers www.ti.
EMAC Module Registers www.ti.com 5.50.15 Broadcast Transmit Frames Register (TXBCASTFRAMES) The total number of good broadcast frames transmitted on the EMAC. A good broadcast frame is defined as having all of the following: • Any data or MAC control frame destined for address FF-FF-FF-FF-FF-FFh only • Was of any length • Had no late or excessive collisions, no carrier loss, and no underrun 5.50.
EMAC Module Registers www.ti.com 5.50.20 Transmit Single Collision Frames Register (TXSINGLECOLL) The total number of frames transmitted on the EMAC that experienced exactly one collision. Such a frame is defined as having all of the following: • Was any data or MAC control frame destined for any unicast, broadcast, or multicast address • Was any size • Had no carrier loss and no underrun • Experienced one collision before successful transmission. The collision was not late.
EMAC Module Registers www.ti.com 5.50.25 Transmit Carrier Sense Errors Register (TXCARRIERSENSE) The total number of frames on the EMAC that experienced carrier loss. Such a frame is defined as having all of the following: • Was any data or MAC control frame destined for any unicast, broadcast, or multicast address • Was any size • The carrier sense condition was lost or never asserted when transmitting the frame (the frame is not retransmitted) CRC errors and underrun have no effect on this statistic. 5.
EMAC Module Registers www.ti.com 5.50.30 Transmit and Receive 256 to 511 Octet Frames Register (FRAME256T511) The total number of 256-byte to 511-byte frames received and transmitted on the EMAC.
EMAC Module Registers www.ti.com 5.50.34 Receive FIFO or DMA Start of Frame Overruns Register (RXSOFOVERRUNS) The total number of frames received on the EMAC that had either a FIFO or DMA start of frame (SOF) overrun.
www.ti.com Appendix A Glossary Broadcast MAC Address— A special Ethernet MAC address used to send data to all Ethernet devices on the local network. The broadcast address is FFh-FFh-FFh-FFh-FFh-FFh. The LSB of the first byte is odd, qualifying it as a group address; however, its value is reserved for broadcast. It is classified separately by the EMAC. Descriptor (Packet Buffer Descriptor)— A small memory structure that describes a larger block of memory in terms of size, location, and state.
Appendix A www.ti.com Multicast MAC Address— A class of MAC address that sends a packet to potentially more than one recipient. A group address is specified by setting the LSB of the first MAC address byte to 1. Thus, 01h-02h-03h-04h-05h-06h is a valid multicast address. Typically, an Ethernet MAC looks for only certain multicast addresses on a network to reduce traffic load. The multicast address list of acceptable packets is specified by the application.
www.ti.com Appendix B Revision History Table 88 lists the changes made since the previous version of this document. Table 88. Document Revision History Reference Figure 2 Additions/Modifications/Deletions Changed figure. Section 2.5.2 Changed first paragraph. Section 2.5.3 Changed third paragraph.
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