Digital Media System-on-Chip (DMSoC) Product Preview

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PRODUCT PREVIEW
PCLK
(Positive Edge Clocking)
PCLK
(Negative Edge Clocking)
7,9
HD/VD
CI[7:0]/YI[7:0]/
CCD[13:0]
8,10
11,13
12,14
5
6
C_WE/C_FIELD
PCLK
(PositiveEdgeClocking)
15
16
23
24
CI[7:0]/YI[7:0]/
CCD[13:0]
C_WE/C_FIELD
PCLK
(PositiveEdgeClocking)
TMS320DM355
Digital Media System-on-Chip (DMSoC)
SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007
Figure 5-24. VPFE (CCD) Slave Mode Input Data Timing
Table 5-19. Timing Requirements for VPFE (CCD) Master Mode
(1)
(see Figure 5-25 )
DM355
NO. UNIT
MIN MAX
15 t
su(CCDV-PCLK)
Setup time, CCD valid before PCLK edge 3 ns
16 t
h(PCLK-CCDV)
Hold time, CCD valid after PCLK edge 2 ns
23 t
su(CWEV-PCLK)
Setup time, C_WE valid before PCLK edge 3 ns
24 t
h(PCLK-CWEV)
Hold time, C_WE valid after PCLK edge 2 ns
(1) The VPFE may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode the
rising edge of PCLK is referenced. When in negative edge clocking mode the falling edge of PCLK is referenced.
Figure 5-25. VPFE (CCD) Master Mode Input Data Timing
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