Digital Media System-on-Chip (DMSoC) Product Preview

www.ti.com
PRODUCT PREVIEW
1
PCLK
2
3
7
5
6
4
8
EXTCLK
4
8
TMS320DM355
Digital Media System-on-Chip (DMSoC)
SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007
• Internal Color Bar Generation (100%/75%)
• YUV/RGB modes support HDTV output (720p/1080i) with 74.25 MHz external clock input
5.9.2.3 VPBE Electrical Data/Timing
Table 5-21. Timing Requirements for VPBE CLK Inputs (see Figure 5-27 )
DM355
NO. UNIT
MIN MAX
1 t
c(PCLK)
Cycle time, PCLK
(1)
13.33 160 ns
2 t
w(PCLKH)
Pulse duration, PCLK high 5.7 ns
3 t
w(PCLKL)
Pulse duration, PCLK low 5.7 ns
4 t
t(PCLK)
Transition time, PCLK 3 ns
5 t
c(EXTCLK)
Cycle time, EXTCLK 13.33 160 ns
6 t
w(EXTCLKH)
Pulse duration, EXTCLK high 5.7 ns
7 t
w(EXTCLKL)
Pulse duration, EXTCLK low 5.7 ns
8 t
t(EXTCLK)
Transition time, EXTCLK 3 ns
(1) When the CCDC is used, the PCLK frequency must be less than or equal to half the VPSS clock frequency—i.e., PCLK ≤ SYSCLK4/2.
Figure 5-27. VPBE PCLK and EXTCLK Timing
Table 5-22. Timing Requirements for VPBE Control Input With Respect to PCLK and EXTCLK
(1) (2) (3)
(see
Figure 5-28 )
DM355
NO. UNIT
MIN MAX
9 t
su(VCTLV-VCLKIN)
Setup time, VCTL valid before VCLKIN edge 2 ns
10 t
h(VCLKIN-VCTLV)
Hold time, VCTL valid after VCLKIN edge 1 ns
(1) The VPBE may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode, the
rising edge of VCLKIN is referenced. When in negative edge clocking mode, the falling edge of VCLKIN is referenced.
(2) VCTL = HSYNC, VSYNC, and FIELD
(3) VCLKIN = PCLK or EXTCLK
Peripheral Information and Electrical Specifications122 Submit Documentation Feedback