Digital Media System-on-Chip (DMSoC) Product Preview

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SPI_CLK
(ClockPolarity=0)
SPI_CLK
(ClockPolarity=1)
SPI_DI
(Input)
SPI_DO
(Output)
13
MSBIN DATA LSBIN
LSBOUTMSBOUT
DATA
17
15
14
16
SPI_EN
19
18
TMS320DM355
Digital Media System-on-Chip (DMSoC)
SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007
SPI Master Mode Timings (Clock Phase = 1)
Table 5-31. Timing Requirements for SPI Master Mode [Clock Phase = 1] (see Figure 5-38 )
DM355
NO. UNIT
MIN MAX
Setup time, SPI_DI (input) valid before SPI_CLK (output)
13 t
su(DIV-CLKL)
Clock Polarity = 0 .5P + 3 ns
rising edge
Setup time, SPI_DI (in put) valid before SPI_CLK (output)
14 t
su(DIV-CLKH)
Clock Polarity = 1 .5P + 3 ns
falling edge
Hold time, SPI_DI (input) valid after SPI_CLK (output) rising
15 t
h(CLKL-DIV)
Clock Polarity = 0 .5P + 3 ns
edge
Hold time, SPI_DI (input) valid after SPI_CLK (output) falling
16 t
h(CLKH-DIV)
Clock Polarity = 1 .5P + 3 ns
edge
Table 5-32. Switching Characteristics Over Recommended Operating Conditions for SPI Master Mode
[Clock Phase = 1] (see Figure 5-38 )
DM355
NO. PARAMETER UNIT
MIN MAX
Delay time, SPI_CLK (output) falling edge to SPI_DO
17 t
d(CLKL-DOV)
Clock Polarity = 0 -4 5 ns
(output) transition
Delay time, SPI_CLK (output) rising edge to SPI_DO
18 t
d(CLKH-DOV)
Clock Polarity = 1 -4 5 ns
(output) transition
Delay time, SPI_EN[1:0] (output) falling edge to first SPI_CLK (output) rising or falling 2P+.5C
19 t
d(ENL-CLKH/L)
(1)
ns
edge
(1)
20 t
d(CLKL/H-DOHz)
Delay time, SPI_CLK (output) falling or rising edge to SPI_DO (output) high impedance P
(2) (2)
ns
(1) The delay time can be adjusted using the SPI module register C2TDELAY. See the TMS320DM355 DMSoC Serial Peripheral Interface
(SPI) User's Guide (SPRUED4).
(2) The delay time can be adjusted using the SPI module register T2CDELAY. See the TMS320DM355 DMSoC Serial Peripheral Interface
(SPI) User's Guide (SPRUED4).
Figure 5-38. SPI Master Mode External Timing (Clock Phase = 1)
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