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5.13.1 I2C Electrical Data/Timing
10
8
4
3
7
12
5
6
14
2
3
13
Stop Start Repeated
Start
Stop
SDA
SCL
1
11 9
TMS320DM355
Digital Media System-on-Chip (DMSoC)
SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007
5.13.1.1 Inter-Integrated Circuits (I2C) Timing
Table 5-33. Timing Requirements for I2C Timings
(1)
(see Figure 5-39 )
DM355
STANDARD
NO. FAST MODE UNIT
MODE
MIN MAX MIN MAX
1 t
c(SCL)
Cycle time, SCL 10 2.5 μ s
Setup time, SCL high before SDA low (for a repeated START
2 t
su(SCLH-SDAL)
4.7 0.6 μ s
condition)
Hold time, SCL low after SDA low (for a START and a repeated
3 t
h(SCLL-SDAL)
4 0.6 μ s
START condition)
4 t
w(SCLL)
Pulse duration, SCL low 4.7 1.3 μ s
5 t
w(SCLH)
Pulse duration, SCL high 4 0.6 μ s
6 t
su(SDAV-SCLH)
Setup time, SDA valid before SCL high 250 100
(2)
ns
7 t
h(SDA-SCLL)
Hold time, SDA valid after SCL low (For I
2
C bus™ devices) 0
(3)
0
(3)
0.9
(4)
μ s
Pulse duration, SDA high between STOP and START
8 t
w(SDAH)
4.7 1.3 μ s
conditions
9 t
r(SDA)
Rise time, SDA 1000 20 + 0.1C
b
(5)
300 ns
10 t
r(SCL)
Rise time, SCL 1000 20 + 0.1C
b
(5)
300 ns
11 t
f(SDA)
Fall time, SDA 300 20 + 0.1C
b
(5)
300 ns
12 t
f(SCL)
Fall time, SCL 300 20 + 0.1C
b
(5)
300 ns
13 t
su(SCLH-SDAH)
Setup time, SCL high before SDA high (for STOP condition) 4 0.6 μ s
14 t
w(SP)
Pulse duration, spike (must be suppressed) 0 50 ns
15 C
b
(5)
Capacitive load for each bus line 400 400 pF
(1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered
down.
(2) A Fast-mode I
2
C-bus™ device can be used in a Standard-mode I
2
C-bus™ system, but the requirement t
su(SDA-SCLH)
≥ 250 ns must then
be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch
the LOW period of the SCL signal, it must output the next data bit to the SDA line t
r
max + t
su(SDA-SCLH)
= 1000 + 250 = 1250 ns
(according to the Standard-mode I
2
C-Bus Specification) before the SCL line is released.
(3) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V
IHmin
of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
(4) The maximum t
h(SDA-SCLL)
has only to be met if the device does not stretch the low period [t
w(SCLL)
] of the SCL signal.
(5) C
b
= total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
Figure 5-39. I2C Receive Timings
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