Digital Media System-on-Chip (DMSoC) Product Preview

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PRODUCT PREVIEW
TMS320DM355
Digital Media System-on-Chip (DMSoC)
SPRS463A – SEPTEMBER 2007 – REVISED SEPTEMBER 2007
to static current leakage and occurs regardless of the clock rate. Leakage, or standby power, is
unavoidable while power is applied and scales roughly with the operating junction temperatures. Leakage
power can only be avoided by removing power completely from a device or subsystem. The DM355
includes several power management features which are briefly described in Table 12-1. Refer to the ARM
Subsystem User's Guide for more information on power management.
Table 3-17. Power Management Features
Power Management Features Description
Clock Management
Module clock disable Module clocks can be disabled to reduce switching power
Module clock frequency scaling Module clock frequency can be scaled to reduce switching power
PLL power-down The PLLs can be powered-down when not in use to reduce
switching power
ARM Sleep Mode
ARM Wait-for-Interrupt sleep mode Disable ARM clock to reduce active power
System Sleep Modes
Deep Sleep mode Stop all device clocks and power down internal oscillators to reduce
active power to a minimum. Registers and memory are preserved.
I/O Management
USB Phy power-down The USB Phy can be powered-down to reduce USB I/O power
DAC power-down The DAC's can be powered-down to reduce DAC power
DDR self-refresh and power down The DDR / mDDR device can be put into self-refresh and power
down states
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