Network Card User Manual

Ethernet Media Access Controller (EMAC) Registers

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5.28 Receive Channel 0-7 Free Buffer Count Register (RXnFREEBUFFER)

The receive channel 0-7 free buffer count register (RXnFREEBUFFER) is shown in Figure 67 and

described in Table 65.

Figure 67. Receive Channel n Free Buffer Count Register (RXnFREEBUFFER)

31 16

Reserved

R-0

15 0

RXnFREEBUF

WI-0

LEGEND: R = Read only; WI = Write to increment; -n = value after reset

Table 65. Receive Channel n Free Buffer Count Register (RXnFREEBUFFER) Field Descriptions

Bit Field Value Description

31-16 Reserved 0 Reserved

15-0 RXnFREEBUF 0-FFh Receive free buffer count. These bits contain the count of free buffers available. The

RXFILTERTHRESH value is compared with this field to determine if low priority frames should be

filtered. The RXnFLOWTHRESH value is compared with this field to determine if receive flow

control should be issued against incoming packets (if enabled). This is a write-to-increment field.

This field rolls over to 0 on overflow.

If hardware flow control or QOS is used, the host must initialize this field to the number of available

buffers (one register per channel). The EMAC decrements the associated channel register for each

received frame by the number of buffers in the received frame. The host must write this field with

the number of buffers that have been freed due to host processing.

108

Ethernet Media Access Controller (EMAC)/Management Data Input/Output SPRUFI5B–March 2009–Revised December 2010

(MDIO)

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