Network Card User Manual

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Architecture

2.15.2 Hardware Reset Considerations

When a hardware reset occurs, the EMAC peripheral has its register values reset and all the components

return to their default state. After the hardware reset, the EMAC needs to be initialized before being able

to resume its data transmission, as described in Section 2.16.

A hardware reset is the only means of recovering from the error interrupts (HOSTPEND), which are

triggered by errors in packet buffer descriptors. Before doing a hardware reset, you should inspect the

error codes in the MAC status register (MACSTATUS) that gives information about the type of software

error that needs to be corrected. For detailed information on error interrupts, see Section 2.17.1.5.

2.16 Initialization

2.16.1 Enabling the EMAC/MDIO Peripheral

When the device is powered on, the EMAC peripheral is in a disabled state. Before any EMAC specific

initialization can take place, the EMAC needs to be enabled; otherwise, its registers cannot be written and

the reads will all return a value of zero.

The EMAC/MDIO is enabled through the Power and Sleep Controller (PSC) registers. For information on

how to enable the EMAC peripheral from the PSC, see the TMS320DM365 Digital Media System-on-Chip

(DMSoC) ARM Subsystem Reference Guide (SPRUFG5) (SPRUFB3).

When first enabled, the EMAC peripheral registers are set to their default values. After enabling the

peripheral, you may proceed with the module specific initialization.

2.16.2 EMAC Control Module Initialization

The EMAC control module is used for global interrupt enable, and to pace back-to-back interrupts using

an interrupt retrigger count based on the peripheral clock (PLL1/6). There is also an 8K block of RAM local

to the EMAC that is used to hold packet buffer descriptors.

Note that although the EMAC control module and the EMAC module have slightly different functions, in

practice, the type of maintenance performed on the EMAC control module is more commonly conducted

from the EMAC module software (as opposed to the MDIO module).

The initialization of the EMAC control module consists of two parts:

1. Configuration of the interrupt to the CPU.

2. Initialization of the EMAC control module:

• Setting the registers related to interrupt pacing. This applies only to RXPulse and TXPulse

interrupts. By default, interrupts pacing is disabled. If pacing is enabled by programming the EMAC

control module interrupt control register (CMINTCTRL), then the CMTXINTMAX and

CMRXINTMAX registers have to be programmed, to indicate the maximum number of TX_PULSE

and RX_PULSE interrupts per millisecond.

• Initializing the EMAC and MDIO modules.

• Enabling interrupts in the EMAC control module using the EMAC control module interrupt control

registers (CMRXTHRESHINTEN, CMRXINTEN, CMTXINTEN, and CMMISCINTEN).

When using the register-level CSL, the code to perform the actions associated with the second part may

appear as in Example 4.

The process of mapping the EMAC interrupts to one of the CPU’s interrupts is done using the ARM

interrupt controller. Once the interrupt is mapped to a CPU interrupt, general masking and unmasking of

the interrupt (to control reentrancy) should be done at the chip level by manipulating the interrupt enable

mask.

SPRUFI5B–March 2009–Revised December 2010 Ethernet Media Access Controller (EMAC)/Management Data Input/Output

(MDIO)

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