Network Card User Manual

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2.17.2 MDIO Module Interrupt Events and Requests
The MDIO module generates two interrupt events:
• LINKINT: Serial interface link change interrupt. Indicates a change in the state of the PHY link
• USERINT: Serial interface user command event complete interrupt
2.17.2.1 Link Change Interrupt
The MDIO module asserts a link change interrupt (LINKINT) if there is a change in the link state of the
PHY corresponding to the address in the PHYADRMON bit in the MDIO user PHY select register n
(USERPHYSELn), and if the LINKINTENB bit is also set in USERPHYSELn. This interrupt event is also
captured in the LINKINTRAW bit in the MDIO link status change interrupt register (LINKINTRAW).
LINKINTRAW bits 0 and 1 correspond to USERPHYSEL0 and USERPHYSEL1, respectively.
When the interrupt is enabled and generated, the corresponding LINKINTMASKED bit is also set in the
MDIO link status change interrupt register (LINKINTMASKED). The interrupt is cleared by writing back
the same bit to LINKINTMASKED (write to clear).
2.17.2.2 User Access Completion Interrupt
When the GO bit in one of the MDIO user access registers (USERACCESSn) transitions from 1 to 0
(indicating completion of a user access) and the corresponding USERINTMASKSET bit in the MDIO
user command complete interrupt mask set register (USERINTMASKSET) corresponding to
USERACCESS0 or USERACCESS1 is set, a user access completion interrupt (USERINT) is asserted.
This interrupt event is also captured in the USERINTRAW bit in the MDIO user command complete
interrupt register (USERINTRAW). USERINTRAW bits 0 and bit 1 correspond to USERACCESS0 and
USERACCESS1, respectively.
When the interrupt is enabled and generated, the corresponding USERINTMASKED bit is also set in
the MDIO user command complete interrupt register (USERINTMASKED). The interrupt is cleared by
writing back the same bit to USERINTMASKED (write to clear).
2.17.3 Proper Interrupt Processing
All the interrupts signaled from the EMAC and MDIO modules are level driven, so if they remain active,
their level remains constant; the CPU core requires edge-triggered interrupts. In order to properly
convert the level-driven interrupt signal to an edge-triggered signal, the application software must make
use of the interrupt control logic contained in the EMAC control module.
Section 2.7.3 discusses the interrupt control contained in the EMAC control module. For safe interrupt
processing, upon entry to the ISR, the software application should disable interrupts using the EMAC
control module interrupt control registers (CMRXTHRESHINTEN, CMRXINTEN, CMTXINTEN, and
CMMISCINTEN), and then reenable them upon leaving the ISR. If any interrupt signals are active at
that time, this creates another rising edge on the interrupt signal going to the CPU interrupt controller,
thus triggering another interrupt. The EMAC control module also implements the optional interrupt
pacing.
2.17.4 Interrupt Multiplexing
The EMAC control module combines all the different interrupt signals from both the EMAC and MDIO
modules and generates four separate interrupt signals that are wired to the ARM interrupt controller
(AINTC) as seen in Figure 11. Once this interrupt is generated, the reason for the interrupt can be read
from the MAC input vector register (MACINVECTOR) located in the EMAC memory map.
MACINVECTOR combines the status of the following 28 interrupt signals: TXPENDn, RXPENDn,
RXTHRESHPENDn, STATPEND, HOSTPEND, LINKINT, and USERINT.The four interrupt signals are
multiplexed with the GPIO 8-11 interrupts. For programming the ARM interrupt controller for
demultiplexing the EMAC interrupts please refer to TMS320DM365 Digital Media System-on-Chip
(DMSoC) ARM Subsystem Reference Guide (SPRUFG5).
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Ethernet Media Access Controller (EMAC)/Management Data Input/Output SPRUFI5B–March 2009–Revised December 2010
(MDIO)
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