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Ethernet Media Access Controller (EMAC) Registers www.ti.com
5.14 Receive Interrupt Status (Masked) Register (RXINTSTATMASKED)
The receive interrupt status (masked) register (RXINTSTATMASKED) is shown in Figure 53 and
described in Table 51.
Figure 53. Receive Interrupt Status (Masked) Register (RXINTSTATMASKED)
31 16
Reserved
R-0
15 8
Reserved
R-0
7 6 5 4 3 2 1 0
RX7PEND RX6PEND RX5PEND RX4PEND RX3PEND RX2PEND RX1PEND RX0PEND
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
LEGEND: R = Read only; -n = value after reset
Table 51. Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) Field Descriptions
Bit Field Value Description
31-8 Reserved 0 Reserved
7 RX7PEND 0-1 RX7PEND masked interrupt read
6 RX6PEND 0-1 RX6PEND masked interrupt read
5 RX5PEND 0-1 RX5PEND masked interrupt read
4 RX4PEND 0-1 RX4PEND masked interrupt read
3 RX3PEND 0-1 RX3PEND masked interrupt read
2 RX2PEND 0-1 RX2PEND masked interrupt read
1 RX1PEND 0-1 RX1PEND masked interrupt read
0 RX0PEND 0-1 RX0PEND masked interrupt read
96
Ethernet Media Access Controller (EMAC)/Management Data Input/Output SPRUFI5B–March 2009–Revised December 2010
(MDIO)
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