DDR2 Memory Controller User's Guide

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DDR_CLK
DDR_CKE
DDR_CS
DDR_RAS
DDR_WE
DDR_A[12,11, 9:0]
DDR_BA[2:0]
DDR_DQM[3:0]
DEAC
DDR_A[10]
DDR_CAS
DDR_CLK
Peripheral Architecture
The DEAC command closes a single bank of memory specified by the bank select signals. Figure 6 shows
the timings diagram for a DEAC command.
Figure 6. DEAC Command
SPRU986B – November 2007 DDR2 Memory Controller 15
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