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5.47 Transmit Channel 0-7 Completion Pointer Register (TX nCP)
5.48 Receive Channel 0-7 Completion Pointer Register (RX nCP)
Ethernet Media Access Controller (EMAC) Registers
The transmit channel 0-7 completion pointer register (TX nCP) is shown in Figure 73 and described in
Table 72 .
Figure 73. Transmit Channel n Completion Pointer Register (TX nCP)
31 16
TX nCP
R/W-x
15 0
TX nCP
R/W-x
LEGEND: R/W = Read/Write; - n = value after reset; -x = value is indeterminate after reset
Table 72. Transmit Channel n Completion Pointer Register (TX nCP) Field Descriptions
Bit Field Value Description
31-0 TX nCP 0-FFFF FFFFh Transmit channel n completion pointer register is written by the host with the buffer descriptor
address for the last buffer processed by the host during interrupt processing. The EMAC uses the
value written to determine if the interrupt should be deasserted.
The receive channel 0-7 completion pointer register (RX nCP) is shown in Figure 74 and described in
Table 73 .
Figure 74. Receive Channel n Completion Pointer Register (RX nCP)
31 16
RX nCP
R/W-x
15 0
RX nCP
R/W-x
LEGEND: R/W = Read/Write; - n = value after reset; -x = value is indeterminate after reset
Table 73. Receive Channel n Completion Pointer Register (RX nCP) Field Descriptions
Bit Field Value Description
31-0 RX nCP 0-FFFF FFFFh Receive channel n completion pointer register is written by the host with the buffer descriptor
address for the last buffer processed by the host during interrupt processing. The EMAC uses the
value written to determine if the interrupt should be deasserted.
SPRU941A – April 2007 Ethernet Media Access Controller (EMAC)/ 107
Management Data Input/Output (MDIO)
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