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4.9 MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET)
MDIO Registers
The MDIO user command complete interrupt mask set register (USERINTMASKSET) is shown in
Figure 21 and described in Table 19 .
Figure 21. MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET)
31 16
Reserved
R-0
15 2 1 0
Reserved USERINTMASKSET
R-0 R/WS-0
LEGEND: R = Read only; R/W = Read/Write; WS = Write 1 to set; - n = value after reset
Table 19. MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET)
Field Descriptions
Bit Field Value Description
31-2 Reserved 0 Reserved
1-0 USERINTMASKSET MDIO user interrupt mask set for USERINTMASKED[1:0], respectively. Setting a bit to 1 will
enable MDIO user command complete interrupts for that particular USERACCESS register.
MDIO user interrupt for a particular USERACCESS register is disabled if the corresponding bit
is 0. USERINTMASKSET[0] and USERINTMASKSET[1] correspond to USERACCESS0 and
USERACCESS1, respectively. Writing a 0 to this register has no effect.
0 MDIO user command complete interrupts for the MDIO user access register n
(USERACCESS n) are disabled.
1 MDIO user command complete interrupts for the MDIO user access register n
(USERACCESS n) are enabled.
62 Ethernet Media Access Controller (EMAC)/ SPRU941A – April 2007
Management Data Input/Output (MDIO)
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