User Guide

53 Receive Channel n Free Buffer Count Register (RX nFREEBUFFER) .............................................. 93
54 MAC Control Register (MACCONTROL) ................................................................................ 94
55 MAC Status Register (MACSTATUS) ................................................................................... 96
56 Emulation Control Register (EMCONTROL) ............................................................................ 98
57 FIFO Control Register (FIFOCONTROL) ............................................................................... 98
58 MAC Configuration Register (MACCONFIG) ........................................................................... 99
59 Soft Reset Register (SOFTRESET) ..................................................................................... 99
60 MAC Source Address Low Bytes Register (MACSRCADDRLO)................................................... 100
61 MAC Source Address High Bytes Register (MACSRCADDRHI) ................................................... 100
62 MAC Hash Address Register 1 (MACHASH1) ........................................................................ 101
63 MAC Hash Address Register 2 (MACHASH2) ........................................................................ 101
64 Back Off Random Number Generator Test Register (BOFFTEST) ................................................ 102
65 Transmit Pacing Algorithm Test Register (TPACETEST) ........................................................... 102
66 Receive Pause Timer Register (RXPAUSE) .......................................................................... 103
67 Transmit Pause Timer Register (TXPAUSE) .......................................................................... 103
68 MAC Address Low Bytes Register (MACADDRLO) .................................................................. 104
69 MAC Address High Bytes Register (MACADDRHI) .................................................................. 104
70 MAC Index Register (MACINDEX) ..................................................................................... 105
71 Transmit Channel n DMA Head Descriptor Pointer Register (TX nHDP) .......................................... 106
72 Receive Channel n DMA Head Descriptor Pointer Register (RX nHDP) .......................................... 106
73 Transmit Channel n Completion Pointer Register (TX nCP) ......................................................... 107
74 Receive Channel n Completion Pointer Register (RX nCP) ......................................................... 107
75 Statistics Register ......................................................................................................... 108
SPRU941A – April 2007 List of Figures 7
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