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5.15 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR)
Ethernet Media Access Controller (EMAC) Registers
The receive interrupt mask clear register (RXINTMASKCLEAR) is shown in Figure 41 and described in
Table 40 .
Figure 41. Receive Interrupt Mask Clear Register (RXINTMASKCLEAR)
31 16
Reserved
R-0
15 8
Reserved
R-0
7 6 5 4 3 2 1 0
RX7MASK RX6MASK RX5MASK RX4MASK RX3MASK RX2MASK RX1MASK RX0MASK
R/WC-0 R/WC-0 R/WC-0 R/WC-0 R/WC-0 R/WC-0 R/WC-0 R/WC-0
LEGEND: R = Read only; R/W = Read/Write; WC = Write 1 to clear, write of 0 has no effect; - n = value after reset
Table 40. Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) Field Descriptions
Bit Field Value Description
31-8 Reserved 0 Reserved
7 RX7MASK 0-1 Receive channel 7 mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect.
6 RX6MASK 0-1 Receive channel 6 mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect.
5 RX5MASK 0-1 Receive channel 5 mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect.
4 RX4MASK 0-1 Receive channel 4 mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect.
3 RX3MASK 0-1 Receive channel 3 mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect.
2 RX2MASK 0-1 Receive channel 2 mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect.
1 RX1MASK 0-1 Receive channel 1 mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect.
0 RX0MASK 0-1 Receive channel 0 mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect.
SPRU941A – April 2007 Ethernet Media Access Controller (EMAC)/ 83
Management Data Input/Output (MDIO)
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