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5.16 MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW)
5.17 MAC Interrupt Status (Masked) Register (MACINTSTATMASKED)
Ethernet Media Access Controller (EMAC) Registers
The MAC interrupt status (unmasked) register (MACINTSTATRAW) is shown in Figure 42 and
described in Table 41 .
Figure 42. MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW)
31 16
Reserved
R-0
15 2 1 0
Reserved HOSTPEND STATPEND
R-0 R-0 R-0
LEGEND: R = Read only; - n = value after reset
Table 41. MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) Field Descriptions
Bit Field Value Description
31-2 Reserved 0 Reserved
1 HOSTPEND 0-1 Host pending interrupt (HOSTPEND); raw interrupt read (before mask).
0 STATPEND 0-1 Statistics pending interrupt (STATPEND); raw interrupt read (before mask).
The MAC interrupt status (masked) register (MACINTSTATMASKED) is shown in Figure 43 and
described in Table 42 .
Figure 43. MAC Interrupt Status (Masked) Register (MACINTSTATMASKED)
31 16
Reserved
R-0
15 2 1 0
Reserved HOSTPEND STATPEND
R-0 R-0 R-0
LEGEND: R = Read only; - n = value after reset
Table 42. MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) Field Descriptions
Bit Field Value Description
31-2 Reserved 0 Reserved
1 HOSTPEND 0-1 Host pending interrupt (HOSTPEND); masked interrupt read.
0 STATPEND 0-1 Statistics pending interrupt (STATPEND); masked interrupt read.
84 Ethernet Media Access Controller (EMAC)/ SPRU941A – April 2007
Management Data Input/Output (MDIO)
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