User Guide

50 Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) Field Descriptions ......... 92
51 Receive Channel n Flow Control Threshold Register (RX nFLOWTHRESH) Field Descriptions ................ 92
52 Receive Channel n Free Buffer Count Register (RX nFREEBUFFER) Field Descriptions ....................... 93
53 MAC Control Register (MACCONTROL) Field Descriptions ......................................................... 94
54 MAC Status Register (MACSTATUS) Field Descriptions ............................................................. 96
55 Emulation Control Register (EMCONTROL) Field Descriptions ..................................................... 98
56 FIFO Control Register (FIFOCONTROL) Field Descriptions ......................................................... 98
57 MAC Configuration Register (MACCONFIG) Field Descriptions ..................................................... 99
58 Soft Reset Register (SOFTRESET) Field Descriptions ............................................................... 99
59 MAC Source Address Low Bytes Register (MACSRCADDRLO) Field Descriptions ............................ 100
60 MAC Source Address High Bytes Register (MACSRCADDRHI) Field Descriptions............................. 100
61 MAC Hash Address Register 1 (MACHASH1) Field Descriptions ................................................. 101
62 MAC Hash Address Register 2 (MACHASH2) Field Descriptions ................................................. 101
63 Back Off Test Register (BOFFTEST) Field Descriptions ............................................................ 102
64 Transmit Pacing Algorithm Test Register (TPACETEST) Field Descriptions ..................................... 102
65 Receive Pause Timer Register (RXPAUSE) Field Descriptions .................................................... 103
66 Transmit Pause Timer Register (TXPAUSE) Field Descriptions ................................................... 103
67 MAC Address Low Bytes Register (MACADDRLO) Field Descriptions ........................................... 104
68 MAC Address High Bytes Register (MACADDRHI) Field Descriptions ............................................ 104
69 MAC Index Register (MACINDEX) Field Descriptions ............................................................... 105
70 Transmit Channel n DMA Head Descriptor Pointer Register (TX nHDP) Field Descriptions .................... 106
71 Receive Channel n DMA Head Descriptor Pointer Register (RX nHDP) Field Descriptions .................... 106
72 Transmit Channel n Completion Pointer Register (TX nCP) Field Descriptions .................................. 107
73 Receive Channel n Completion Pointer Register (RX nCP) Field Descriptions ................................... 107
A-1 Physical Layer Definitions ............................................................................................... 118
B-1 Document Revision History .............................................................................................. 119
SPRU941A – April 2007 List of Tables 9
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