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5.32 MAC Configuration Register (MACCONFIG)
5.33 Soft Reset Register (SOFTRESET)
Ethernet Media Access Controller (EMAC) Registers
The MAC configuration register (MACCONFIG) is shown in Figure 58 and described in Table 57 .
Figure 58. MAC Configuration Register (MACCONFIG)
31 24 23 16
TXCELLDEPTH RXCELLDEPTH
R-3h R-3h
15 8 7 0
ADDRESSTYPE MACCFIG
R-1 R-1
LEGEND: R = Read only; - n = value after reset
Table 57. MAC Configuration Register (MACCONFIG) Field Descriptions
Bit Field Value Description
31-24 TXCELLDEPTH 3h Transmit cell depth. These bits indicate the number of cells in the transmit FIFO.
23-16 RXCELLDEPTH 3h Receive cell depth. These bits indicate the number of cells in the receive FIFO.
15-8 ADDRESSTYPE 1h Address type
7-0 MACCFIG 1h MAC configuration value
The soft reset register (SOFTRESET) is shown in Figure 59 and described in Table 58 .
Figure 59. Soft Reset Register (SOFTRESET)
31 16
Reserved
R-0
15 1 0
Reserved SOFTRESET
R-0 R/W-0
LEGEND: R = Read only; R/W = Read/Write; - n = value after reset
Table 58. Soft Reset Register (SOFTRESET) Field Descriptions
Bit Field Value Description
31-1 Reserved 0 Reserved
0 SOFTRESET Software reset. Writing a 1 to this bit causes the EMAC logic to be reset. Software reset occurs
when the receive and transmit DMA controllers are in an idle state to avoid locking up the
Configuration bus. After writing a 1 to this bit, it may be polled to determine if the reset has
occurred. If a 1 is read, the reset has not yet occurred. If a 0 is read, then a reset has occurred.
0 A software reset has not occurred.
1 A software reset has occurred.
SPRU941A – April 2007 Ethernet Media Access Controller (EMAC)/ 99
Management Data Input/Output (MDIO)
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