TMS320DM644x DMSoC Multimedia Card (MMC)/Secure Digital (SD) Card Controller User's Guide

Contents
Preface ............................................................................................................................... 7
1 Introduction ................................................................................................................ 9
1.1 Purpose of the Peripheral ....................................................................................... 9
1.2 Features ........................................................................................................... 9
1.3 Functional Block Diagram ....................................................................................... 9
1.4 Supported Use Case Statement .............................................................................. 10
1.5 Industry Standard(s) Compliance Statement ............................................................... 10
2 Peripheral Architecture .............................................................................................. 10
2.1 Clock Control .................................................................................................... 12
2.2 Signal Descriptions ............................................................................................. 13
2.3 Protocol Descriptions........................................................................................... 13
2.4 Data Flow in the Input/Output FIFO .......................................................................... 15
2.5 Data Flow in the Data Registers (MMCDRR and MMCDXR) ............................................. 17
2.6 FIFO Operation During Card Read Operation .............................................................. 19
2.7 FIFO Operation During Card Write Operation .............................................................. 21
2.8 Reset Considerations .......................................................................................... 23
2.9 Initialization ...................................................................................................... 23
2.10 Interrupt Support ................................................................................................ 27
2.11 DMA Event Support ............................................................................................ 28
2.12 Power Management ............................................................................................ 28
2.13 Emulation Considerations ..................................................................................... 28
3 Procedures for Common Operations ........................................................................... 29
3.1 Card Identification Operation .................................................................................. 29
3.2 MMC/SD Mode Single-Block Write Operation Using CPU ................................................ 32
3.3 MMC/SD Mode Single-Block Write Operation Using the EDMA ......................................... 34
3.4 MMC/SD Mode Single-Block Read Operation Using the CPU ........................................... 34
3.5 MMC/SD Mode Single-Block Read Operation Using EDMA .............................................. 35
3.6 MMC/SD Mode Multiple-Block Write Operation Using CPU .............................................. 36
3.7 MMC/SD Mode Multiple-Block Write Operation Using EDMA ............................................ 38
3.8 MMC/SD Mode Multiple-Block Read Operation Using CPU .............................................. 38
3.9 MMC/SD Mode Multiple-Block Read Operation Using EDMA ............................................ 39
4 Registers .................................................................................................................. 40
4.1 MMC Control Register (MMCCTL) ........................................................................... 41
4.2 MMC Memory Clock Control Register (MMCCLK) ......................................................... 42
4.3 MMC Status Register 0 (MMCST0) .......................................................................... 43
4.4 MMC Status Register 1 (MMCST1) .......................................................................... 45
4.5 MMC Interrupt Mask Register (MMCIM) ..................................................................... 46
4.6 MMC Response Time-Out Register (MMCTOR) ........................................................... 47
4.7 MMC Data Read Time-Out Register (MMCTOD) .......................................................... 48
4.8 MMC Block Length Register (MMCBLEN) .................................................................. 49
4.9 MMC Number of Blocks Register (MMCNBLK) ............................................................ 50
4.10 MMC Number of Blocks Counter Register (MMCNBLC) .................................................. 50
4.11 MMC Data Receive Register (MMCDRR) ................................................................... 51
4.12 MMC Data Transmit Register (MMCDXR) .................................................................. 51
SPRUE30B – September 2006 Table of Contents 3
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