TMS320DM644x DMSoC Multimedia Card (MMC)/Secure Digital (SD) Card Controller User's Guide

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4.6 MMC Response Time-Out Register (MMCTOR)

Registers

Table 10. MMC Interrupt Mask Register (MMCIM) Field Descriptions (continued)

Bit Field Value Description

3 ETOUTRD Read-data time-out event (TOUTRD) interrupt enable.

0 Read-data time-out event interrupt is disabled.

1 Read-data time-out event interrupt is enabled.

2 ERSPDNE Command/response done (RSPDNE) interrupt enable.

0 Command/response done interrupt is disabled.

1 Command/response done interrupt is enabled.

1 EBSYDNE Busy done (BSYDNE) interrupt enable.

0 Busy done interrupt is disabled.

1 Busy done interrupt is enabled.

0 EDATDNE Data done (DATDNE) interrupt enable.

0 Data done interrupt is disabled.

1 Data done interrupt is enabled.

The MMC response time-out register (MMCTOR) defines how long the MMC controller waits for a

response from a memory card before recording a time-out condition in the TOUTRS bit of the MMC status

set, an interrupt is generated when the TOUTRS bit is set in MMCST0. If a memory card should require a

longer time-out period than MMCTOR can provide, a software time-out mechanism can be implemented.

The MMC response time-out register (MMCTOR) is shown in Figure 23 and described in Table 11 .

Figure 23. MMC Response Time-Out Register (MMCTOR)

31 16

Reserved

R-0

15 13 12 8 7 0

Reserved TOD_20_16 TOR

R-0 R/W-0 R/W-0

LEGEND: R/W = Read/Write; R = Read only; - n = value after reset

Table 11. MMC Response Time-Out Register (MMCTOR) Field Descriptions

Bit Field Value Description

31-13 Reserved 0 Reserved

12-8 TOD_20_16 0-1Fh Data read time-out count upper 5 bits. Used in conjunction with the TOD_15_0 bits in MMCTOD to

form a 21-bit count. See MMCTOD (Section 4.7 ).

7-0 TOR 0-FFh Time-out count for response.

0 No time out

1-FFh 1 CLK clock cycle to 255 CLK clock cycles

SPRUE30B – September 2006 Multimedia Card (MMC)/Secure Digital (SD) Card Controller 47

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