TMS320DM644x DMSoC Multimedia Card (MMC)/Secure Digital (SD) Card Controller User's Guide

List of Figures
1 MMC/SD Card Controller Block Diagram ............................................................................... 10
2 MMC/SD Controller Interface Diagram .................................................................................. 11
3 MMC Configuration and SD Configuration Diagram ................................................................... 11
4 MMC/SD Controller Clocking Diagram .................................................................................. 12
5 MMC/SD Mode Write Sequence Timing Diagram ..................................................................... 14
6 MMC/SD Mode Read Sequence Timing Diagram ..................................................................... 15
7 FIFO Operation Diagram .................................................................................................. 16
8 Little-Endian Access to MMCDXR/MMCDRR from the ARM CPU or the EDMA .................................. 17
9 Big-Endian Access to MMCDXR/MMCDRR from the ARM CPU or the EDMA .................................... 18
10 FIFO Operation During Card Read Diagram ........................................................................... 20
11 FIFO Operation During Card Write Diagram ........................................................................... 22
12 MMC Card Identification Procedure ..................................................................................... 30
13 SD Card Identification Procedure ........................................................................................ 31
14 MMC/SD Mode Single-Block Write Operation .......................................................................... 33
15 MMC/SD Mode Single-Block Read Operation .......................................................................... 35
16 MMC/SD Multiple-Block Write Operation ............................................................................... 37
17 MMC/SD Mode Multiple-Block Read Operation ........................................................................ 39
18 MMC Control Register (MMCCTL) ....................................................................................... 41
19 MMC Memory Clock Control Register (MMCCLK) ..................................................................... 42
20 MMC Status Register 0 (MMCST0) ...................................................................................... 43
21 MMC Status Register 1 (MMCST1) ...................................................................................... 45
22 MMC Interrupt Mask Register (MMCIM) ................................................................................ 46
23 MMC Response Time-Out Register (MMCTOR) ....................................................................... 47
24 MMC Data Read Time-Out Register (MMCTOD) ...................................................................... 48
25 MMC Block Length Register (MMCBLEN) .............................................................................. 49
26 MMC Number of Blocks Register (MMCNBLK) ........................................................................ 50
27 MMC Number of Blocks Counter Register (MMCNBLC) .............................................................. 50
28 MMC Data Receive Register (MMCDRR)............................................................................... 51
29 MMC Data Transmit Register (MMCDXR) .............................................................................. 51
30 MMC Command Register (MMCCMD) .................................................................................. 52
31 Command Format .......................................................................................................... 53
32 MMC Argument Register (MMCARGHL) ................................................................................ 54
33 MMC Response Register 0 and 1 (MMCRSP01) ...................................................................... 55
34 MMC Response Register 2 and 3 (MMCRSP23) ...................................................................... 55
35 MMC Response Register 4 and 5 (MMCRSP45) ...................................................................... 55
36 MMC Response Register 6 and 7 (MMCRSP67) ...................................................................... 55
37 MMC Data Response Register (MMCDRSP) .......................................................................... 57
38 MMC Command Index Register (MMCCIDX) .......................................................................... 57
39 MMC FIFO Control Register (MMCFIFOCTL) .......................................................................... 58
SPRUE30B – September 2006 List of Figures 5
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