Computer Hardware User Manual

Architecture

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2.5.5.2 Asynchronous Write Operations (Select Strobe Mode)

An asynchronous write is performed when any of the requesters mentioned in Section 2.2 request a write

to memory in the asynchronous bank of the EMIF. In the event that the write request cannot be serviced

by a single access cycle to the external device, multiple access cycles will be performed by the EMIF until

the entire request is fulfilled. The details of an asynchronous write operation in Select Strobe mode are

described in Table 10 and an example timing diagram of a basic write operation is shown in Figure 7.

NOTE: During the entirety of an asynchronous write operation, the EM_OE pin is driven high.

Table 10. Asynchronous Write Operation in Select Strobe Mode

Time Interval Pin Activity in Select Strobe Mode

Turnaround Once the EMIF receives a write request, the EMIF waits for the programmed number of turnaround cycles

period before proceeding to the setup period of the operation. The number of wait cycles is taken directly from the TA

field of the asynchronous configuration register (ACFGn). There are two exceptions to this rule:

• If the current write operation was directly proceeded by another write operation to the same CS space, no

turnaround cycles are inserted.

• If the current write operation was directly proceeded by a write operation to the same CS space and the TA

field has been cleared to 0, one turnaround cycle will be inserted.

After the EMIF has waited for the turnaround cycles to complete, it proceeds to the setup period of the operation.

Start of setup At the beginning of the setup period:

period

• The setup, strobe, and hold values are set according to the W_SETUP, W_STROBE, and W_HOLD values

in ACFGn.

• The address pins EM_A and EM_BA and the data pins EM_D become valid.

• The EM_RW pin falls to indicate a write (if not already low from a previous operation).

Start of strobe At the beginning of the strobe period:

period

• EM_CS and EM_WE fall

Start of hold At the beginning of the hold period:

period

• EM_CS and EM_WE rise

End of hold At the end of the hold period:

period

• The address pins EM_A and EM_BA become invalid

• The data pins become invalid

• The EM_RW pin rises (if no more operations are required to complete the current request)

The EMIF may be required to issue additional write operations to a device with a small data bus width in order to

complete an entire word access. In this case, the EMIF immediately re-enters the setup period to begin another

operation without incurring the turnaround cycle delay. The setup, strobe, and hold values are not updated in this

case. If the entire word access has been completed, the EMIF returns to its previous state unless another

asynchronous request has been submitted. If this is the case, the EMIF instead enters directly into the

turn-around period for the pending read or write operation.

Asynchronous External Memory Interface (EMIF) SPRUEQ7C–February 2010

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