Output (MDIO) Module User's Guide

ManualsBrandsTexas Instruments ManualsComputer HardwareTMS320DM646x

TMS320DM646x DMSoC

Ethernet Media Access Controller (EMAC)/

Management Data Input/Output (MDIO)

Module

User's Guide

Literature Number: SPRUEQ6

December 2007

Summary of content (135 pages)

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TMS320DM646x DMSoC Ethernet Media Access Controller (EMAC)/ Management Data Input/Output (MDIO) Module User's Guide Literature Number: SPRUEQ6 December 2007
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SPRUEQ6 – December 2007 Submit Documentation Feedback
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Contents Preface.............................................................................................................................. 10 1 Introduction .............................................................................................................. 12 1.1 2 3 ......................................................................................................... 12 1.3 Functional Block Diagram .....................................................................................
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.3 PHY Acknowledge Status Register (ALIVE) ................................................................ 73 4.4 PHY Link Status Register (LINK) ............................................................................. 73 4.5 MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) ............................ 74 .......................... 75 4.7 MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) ................... 76 4.
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.36 MAC Source Address High Bytes Register (MACSRCADDRHI) ....................................... 116 5.37 MAC Hash Address Register 1 (MACHASH1) ............................................................ 117 5.38 MAC Hash Address Register 2 (MACHASH2) ............................................................ 117 5.39 Back Off Test Register (BOFFTEST)....................................................................... 118 ............................................... 118 .................
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List of Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 6 EMAC and MDIO Block Diagram ........................................................................................ Ethernet Configuration—MII Connections .............................................................................. Ethernet Configuration—GMII Connections .......................................................................
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53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) ................................................ 96 Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) ............................................... 97 Receive Interrupt Mask Set Register (RXINTMASKSET) ............................................................. 98 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) ..
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List of Tables 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 8 EMAC and MDIO Signals for MII Interface ............................................................................. EMAC and MDIO Signals for GMII Interface ........................................................................... Ethernet Frame Description ...............................................................................................
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48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 A-1 Transmit Interrupt Mask Set Register (TXINTMASKSET) Field Descriptions ...................................... 93 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) Field Descriptions ................................ 94 MAC Input Vector Register (MACINVECTOR) Field Descriptions ...................................................
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Preface SPRUEQ6 – December 2007 Read This First About This Manual This document provides a functional description of the Ethernet Media Access Controller (EMAC) and physical layer (PHY) device Management Data Input/Output (MDIO) module integrated in the TMS320DM646x Digital Media System-on-Chip. Included are the features of the EMAC and MDIO modules, a discussion of their architecture and operation, how these modules connect to the outside world, and the registers description for each module.
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www.ti.com Related Documentation From Texas Instruments SPRU871 — TMS320C64x+ DSP Megamodule Reference Guide. Describes the TMS320C64x+ digital signal processor (DSP) megamodule. Included is a discussion on the internal direct memory access (IDMA) controller, the interrupt controller, the power-down controller, memory protection, bandwidth management, and the memory and cache.
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User's Guide SPRUEQ6 – December 2007 Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) 1 Introduction This document provides a functional description of the Ethernet Media Access Controller (EMAC) and physical layer (PHY) device Management Data Input/Output (MDIO) module integrated in theTMS320DM646x Digital Media System-on-Chip.
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www.ti.com Introduction • • • 1.3 No-chain mode truncates frame to first buffer for network analysis applications. Emulation support. Loopback mode. Functional Block Diagram Figure 1 shows the three main functional modules of the EMAC/MDIO peripheral: • EMAC control module • EMAC module • MDIO module The EMAC control module is the main interface between the device core processor and the EMAC module and MDIO module.
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www.ti.com Architecture The EMAC and MDIO interrupts are combined within the control module, so only the control module interrupt needs to be monitored by the application software or device driver. The EMAC control module combines the EMAC and MDIO interrupts and generates 4 separate interrupts to the ARM through the ARM interrupt controller. See Section 2.16.4 for details of interrupt multiplex logic of the EMAC control module. 1.
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www.ti.com Architecture 2.2 Memory Map The EMAC peripheral includes internal memory that is used to hold information about the Ethernet packets received and transmitted. This internal RAM is 2K × 32 bits in size. Data can be written to and read from the EMAC internal memory by either the EMAC or the CPU. It is used to store buffer descriptors that are 4-words (16-bytes) deep. This 8K local memory holds enough information to transfer up to 512 Ethernet packets without CPU intervention.
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www.ti.com Architecture Table 1. EMAC and MDIO Signals for MII Interface 16 Signal Type Description MTCLK I Transmit clock (MTCLK). The transmit clock is a continuous clock that provides the timing reference for transmit operations. The MTXD and MTXEN signals are tied to this clock. The clock is generated by the PHY and is 2.5 MHZ at 10 Mbps operation and 25 MHZ at 100 Mbps operation. MTXD[3-0] O Transmit data (MTXD).
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www.ti.com Architecture 2.3.2 Gigabit Media Independent Interface (GMII) Connections Figure 3 shows a device with integrated EMAC and MDIO interfaced via a GMII connection. This interface is available in 10 Mbps, 100 Mbps, and 1000 Mbps modes. The GMII interface supports 10/100/1000 Mbps modes. Only full-duplex mode is available in 1000 Mbps mode. In 10/100 Mbps modes, the GMII interface acts like an MII interface and only the lower 4 bits of data are transferred for each of the data buses.
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www.ti.com Architecture Table 2. EMAC and MDIO Signals for GMII Interface (continued) 18 Signal Type Description MCRS I Carrier sense (MCRS). The MCRS pin is asserted by the PHY when the network is not idle in either transmit or receive. The pin is de-asserted when both transmit and receive are idle. This signal is not necessarily synchronous to MTCLK nor MRCLK. This pin is used in half-duplex operation only. MRCLK I Receive clock (MRCLK).
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www.ti.com Architecture 2.4 Ethernet Protocol Overview Ethernet provides an unreliable, connection-less service to a networking application. A brief overview of the Ethernet protocol is given in the following subsections. For in-depth information on the Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method, which is the Ethernet’s multiple access protocol, see the IEEE 802.3 standard document. 2.4.
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www.ti.com Architecture 2.4.2 Ethernet’s Multiple Access Protocol Nodes in an Ethernet Local Area Network are interconnected by a broadcast channel, as a result, when an EMAC port transmits a frame, all the adapters on the local network receive the frame. Carrier Sense Multiple Access with Collision Detection (CSMA/CD) algorithms are used when the EMAC operates in half-duplex mode.
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www.ti.com Architecture Table 4. Basic Descriptor Description Word Offset Field Field Description 0 Next Descriptor Pointer The next descriptor pointer is used to create a single linked list of descriptors. Each descriptor describes a packet or a packet fragment. When a descriptor points to a single buffer packet or the first fragment of a packet, the start of packet (SOP) flag is set in the flags field.
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www.ti.com Architecture 2.5.2 Transmit and Receive Descriptor Queues The EMAC module processes descriptors in linked list chains as discussed in Section 2.5.1. The lists controlled by the EMAC are maintained by the application software through the use of the head descriptor pointer registers (HDP). Since the EMAC supports eight channels for both transmit and receive, there are eight head descriptor pointer registers for both.
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www.ti.com Architecture 2.5.3 Transmit and Receive EMAC Interrupts The EMAC processes descriptors in linked list chains as discussed in Section 2.5.1, using the linked list queue mechanism discussed in Section 2.5.2. The EMAC synchronizes descriptor list processing through the use of interrupts to the software application. The interrupts are controlled by the application using the interrupt masks, global interrupt enable, and the completion pointer register (CP).
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www.ti.com Architecture 2.5.4 Transmit Buffer Descriptor Format A transmit (TX) buffer descriptor (Figure 7) is a contiguous block of four 32-bit data words aligned on a 32-bit boundary that describes a packet or a packet fragment. Example 1 shows the transmit buffer descriptor described by a C structure. Figure 7.
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www.ti.com Architecture 2.5.4.1 Next Descriptor Pointer The next descriptor pointer points to the 32-bit word aligned memory address of the next buffer descriptor in the transmit queue. This pointer is used to create a linked list of buffer descriptors. If the value of this pointer is zero, then the current buffer is the last buffer in the queue. The software application must set this value prior to adding the descriptor to the active transmit list. This pointer is not altered by the EMAC.
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www.ti.com Architecture 2.5.4.7 End of Packet (EOP) Flag When set, this flag indicates that the descriptor points to a packet buffer that is last for a given packet. In the case of a single fragment packet, both the start of packet (SOP) and EOP flags are set. Otherwise, the descriptor pointing to the last packet buffer for the packet sets the EOP flag. This bit is set by the software application and is not altered by the EMAC. 2.5.4.
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www.ti.com Architecture 2.5.5 Receive Buffer Descriptor Format A receive (RX) buffer descriptor (Figure 8) is a contiguous block of four 32-bit data words aligned on a 32-bit boundary that describes a packet or a packet fragment. Example 2 shows the receive buffer descriptor described by a C structure. 2.5.5.1 Next Descriptor Pointer This pointer points to the 32–bit word aligned memory address of the next buffer descriptor in the receive queue.
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www.ti.com Architecture Example 2. Receive Buffer Descriptor in C Structure Format /* // EMAC Descriptor // // The following is the format of a single buffer descriptor // on the EMAC. */ typedef struct _EMAC_Desc { struct _EMAC_Desc *pNext; /* Pointer to next descriptor in chain */ Uint8 *pBuffer; /* Pointer to data buffer */ Uint32 BufOffLen; /* Buffer Offset(MSW) and Length(LSW) PktFlgLen; /* Packet Flags(MSW) and Length(LSW) */ Uint32 */ } EMAC_Desc; /* Packet Flags 2.5.5.
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www.ti.com Architecture 2.5.5.4 Buffer Length This 16-bit field is used for two purposes: • Before the descriptor is first placed on the receive queue by the application software, the buffer length field is first initialized by the software to have the physical size of the empty data buffer pointed to by the buffer pointer field.
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www.ti.com Architecture 2.5.5.10 Teardown Complete (TDOWNCMPLT) Flag This flag is used when a receive queue is being torn down, or aborted, instead of being filled with received data. This would happen under device driver reset or shutdown conditions. The EMAC sets this bit in the descriptor of the first free buffer when the tear down occurs. No additional queue processing is performed. 2.5.5.
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www.ti.com Architecture 2.5.5.21 No Match (NOMATCH) Flag This flag is set by the EMAC in the SOP buffer descriptor, if the received packet did not pass any of the EMAC’s address match criteria and was not discarded because the RXCAFEN bit was set in the RXMBPENABLE. Although the packet is a valid Ethernet data packet, it was only received because the EMAC is in promiscuous mode. 2.
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www.ti.com Architecture 2.6.3 Interrupt Control The EMAC control module combines multiple interrupt conditions generated by the EMAC and MDIO modules into four separate interrupt signals (Table 5) that are mapped to a CPU interrupt via the CPU interrupt controller. The four separate sources of interrupt can be individually enabled for each channel by the CMRXTHRESHINTEN, CMRXINTEN, CMTXINTEN, and CMMISCINTEN registers. Table 5. EMAC Control Module Interrupts 2.6.3.
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www.ti.com Architecture 2.6.3.3 Receive Threshold Pulse Interrupt The EMAC control module receives the eight individual receive threshold interrupts originating from the EMAC module, one for each of the eight channels, and combines them into a single receive threshold pulse interrupt to the CPU. This receive threshold pulse interrupt is not paced.
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www.ti.com Architecture If the rate of transmit pulse interrupt inputs is much less than the target transmit pulse interrupt rate specified in CMTXINTMAX, then the interrupts are not blocked to the CPU. If the transmit pulse interrupt rate is greater than the specified target rate in CMTXINTMAX, the interrupt is paced at the rate specified in this register, which should be written with a value between 2 and 63 inclusive, indicating the target number of interrupts per 1 ms going to the CPU.
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www.ti.com Architecture 2.7.1.2 Global PHY Detection and Link State Monitoring The MDIO module continuously polls all 32 MDIO addresses in order to enumerate the PHY devices in the system. The module tracks whether or not a PHY on a particular address has responded, and whether or not the PHY currently has a link. Using this information allows the software application to quickly determine which MDIO address the PHY is using. 2.7.1.
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www.ti.com Architecture A round-robin arbitration scheme is used to schedule transactions that may be queued using both USERACCESS0 and USERACCESS1. The application software must check the status of the GO bit in USERACCESSn before initiating a new transaction, to ensure that the previous transaction has completed. The application software can use the ACK bit in USERACCESSn to determine the status of a read transaction. 2.7.2.
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www.ti.com Architecture 2.7.2.4 Example of MDIO Register Access Code The MDIO module uses the MDIO user access register (USERACCESSn) to access the PHY control registers.
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www.ti.com Architecture 2.8 EMAC Module This section discusses the architecture and basic function of the EMAC module. 2.8.1 EMAC Module Components The EMAC module (Figure 11) interfaces to the outside world through the Media Independent Interface (MII) and interfaces to the system core through the EMAC control module.
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www.ti.com Architecture 2.8.1.3 MAC Receiver The MAC receiver detects and processes incoming network frames, de-frames them, and puts them into the receive FIFO. The MAC receiver also detects errors and passes statistics to the statistics RAM. 2.8.1.4 Receive Address This sub-module performs address matching and address filtering based on the incoming packet’s destination address.
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www.ti.com Architecture 2.8.2 EMAC Module Operational Overview After reset, initialization, and configuration, the application software running on the host may initiate transmit operations. Transmit operations are initiated by host writes to the appropriate transmit channel head descriptor pointer contained in the state RAM block. The transmit DMA controller then fetches the first packet in the packet chain from memory.
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www.ti.com Architecture 2.9 Media Independent Interface (MII) The following sections discuss the operation of the Media Independent Interface (MII) in 10 Mbps and 100 Mbps mode. An IEEE 802.3 compliant Ethernet MAC controls the interface. 2.9.1 Data Reception 2.9.1.1 Receive Control Data received from the PHY is interpreted and output to the EMAC receive FIFO.
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www.ti.com Architecture 2.9.1.3.1 Collision-Based Receive Buffer Flow Control Collision-based receive buffer flow control provides a means of preventing frame reception when the EMAC is operating in half-duplex mode (the FULLDUPLEX bit is cleared in MACCONTROL). When receive flow control is enabled and triggered, the EMAC generates collisions for received frames. The jam sequence transmitted is the 12-byte sequence C3.C3.C3.C3.C3.C3.C3.C3.C3.C3.C3.C3h.
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www.ti.com Architecture 2.9.2 Data Transmission The EMAC passes data to the PHY from the transmit FIFO (when enabled). Data is synchronized to the transmit clock rate. Transmission begins when there are TXCELLTHRESH cells of 64 bytes each, or a complete packet, in the FIFO. 2.9.2.1 Transmit Control A jam sequence is output if a collision is detected on a transmit packet. If the collision was late (after the first 64 bytes have been transmitted), the collision is ignored.
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www.ti.com Architecture 2.9.2.6 Transmit Flow Control Incoming pause frames are acted upon, when enabled, to prevent the EMAC from transmitting any further frames. Incoming pause frames are only acted upon when the FULLDUPLEX and TXFLOWEN bits in the MAC control register (MACCONTROL) are set. Pause frames are not acted upon in half-duplex mode. Pause frame action is taken if enabled, but normally the frame is filtered and not transferred to memory.
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www.ti.com Architecture 2.10 Packet Receive Operation 2.10.1 Receive DMA Host Configuration To configure the receive DMA for operation the host must: • Initialize the receive addresses. • Initialize the receive channel n DMA head descriptor pointer registers (RXnHDP) to 0. • Write the MAC address hash n registers (MACHASH1 and MACHASH2), if hash matching multicast addressing is desired.
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www.ti.com Architecture 2.10.3 Receive Address Matching The receive address block can store up to 32 addresses to be filtered or matched. Before enabling packet reception, all the address RAM locations should be initialized, including locations to be unused. The system software is responsible for adding and removing addresses from the RAM. A MAC address location in RAM is 53 bits wide and consists of: • • • • 48 bits of the MAC address.
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www.ti.com Architecture to the appropriate receive channel n free buffer count registers (RXnFREEBUFFER). The EMAC decrements the appropriate channel’s free buffer value for each buffer used. When the host reclaims the frame buffers, the host should write the channel free buffer register with the number of reclaimed buffers (write to increment). There are a maximum of 65,535 free buffers available. RXnFREEBUFFER only needs to be updated by the host if receive QOS or flow control is used. 2.10.
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www.ti.com Architecture 2.10.8 Promiscuous Receive Mode When the promiscuous receive mode is enabled by setting the RXCAFEN bit in the receive multicast/broadcast/promiscuous channel enable register (RXMBPENABLE), nonaddress matching frames that would normally be filtered are transferred to the promiscuous channel. Address matching frames that would normally be filtered due to errors are transferred to the address match channel when the RXCAFEN and RXCEFEN bits in RXMBPENABLE are set.
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www.ti.com Architecture Table 6. Receive Frame Treatment Summary (continued) 2.10.9 Address Match RXCAFEN RXCEFEN RXCMFEN RXCSFEN 1 X 1 1 0 Receive Frame Treatment Proper/oversize/jabber/code/align/CRC data and control frames transferred to address match channel. No undersized/fragment frames are transferred.
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www.ti.com Architecture 2.11 Packet Transmit Operation The transmit DMA is an eight channel interface. Priority between the eight queues may be either fixed or round-robin as selected by the TXPTYPE bit in the MAC control register (MACCONTROL). If the priority type is fixed, then channel 7 has the highest priority and channel 0 has the lowest priority. Round-robin priority proceeds from channel 0 to channel 7. 2.11.
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www.ti.com Architecture Receive overrun is prevented if the receive memory cell latency is less than the time required to transmit a 64-byte cell on the wire (0.512 ms in 1 Gbps mode, 5.12 ms in 100 Mbps mode, or 51.2ms in 10 Mbps mode). The latency time includes any required buffer descriptor reads for the cell data. Latency to descriptor RAM is low because RAM is local to the EMAC, as it is part of the EMAC control module. 2.
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www.ti.com Architecture 2.14.2 Hardware Reset Considerations When a hardware reset occurs, the EMAC peripheral has its register values reset and all the components return to their default state. After the hardware reset, the EMAC needs to be initialized before being able to resume its data transmission, as described in Section 2.15. A hardware reset is the only means of recovering from the error interrupts (HOSTPEND), which are triggered by errors in packet buffer descriptors.
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www.ti.com Architecture Example 4. EMAC Control Module Initialization Code Uint32 tmpval ; /* Disable all the EMAC/MDIO interrupts EmacControlRegs->CONTROL.C_RX_EN EmacControlRegs->CONTROL.C_TX_EN EmacControlRegs->CONTROL.C_RX_THRESH_EN EmacControlRegs->CONTROL.
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www.ti.com Architecture 2.15.3 MDIO Module Initialization The MDIO module is used to initially configure and monitor one or more external PHY devices. Other than initializing the software state machine (details on this state machine can be found in the IEEE 802.3 standard), all that needs to be done for the MDIO module is to enable the MDIO engine and to configure the clock divider. To set the clock divider, supply an MDIO clock of 1 MHZ.
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www.ti.com Architecture 2.15.4 EMAC Module Initialization The EMAC module is used to send and receive data packets over the network. This is done by maintaining up to eight transmit and receive descriptor queues. The EMAC module configuration must also be kept up-to-date based on PHY negotiation results returned from the MDIO module. Most of the work in developing an application or device driver for Ethernet is programming this module.
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www.ti.com Architecture 2.16 Interrupt Support 2.16.
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www.ti.com Architecture 2.16.1.2 Transmit Packet Completion Interrupts The transmit DMA engine has eight channels, with each channel having a corresponding interrupt (TXPENDn). The transmit interrupts are level interrupts that remain asserted until cleared by the CPU. Each of the eight transmit channel interrupts may be individually enabled by setting the corresponding bit in the transmit interrupt mask set register (TXINTMASKSET) to 1.
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www.ti.com Architecture The EMAC write to the completion pointer actually stores the value in the state RAM. The CPU written value does not actually change the register value. The host written value is compared to the register content (which was written by the EMAC) and if the two values are equal then the interrupt is removed; otherwise, the interrupt remains asserted. The host may process multiple packets prior to acknowledging an interrupt, or the host may acknowledge interrupts for every packet. 2.16.
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www.ti.com Architecture 2.16.2 MDIO Module Interrupt Events and Requests The MDIO module generates two interrupt events: • LINKINT: Serial interface link change interrupt. Indicates a change in the state of the PHY link • USERINT: Serial interface user command event complete interrupt 2.16.2.
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www.ti.com Architecture 2.17 Power Management Each of the three main components of the EMAC peripheral can independently be placed in reduced-power modes to conserve power during periods of low activity. The power management of the EMAC peripheral is controlled by the processor Power and Sleep Controller (PSC). The PSC acts as a master controller for power management on behalf of all of the peripherals on the device.
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www.ti.com EMAC Control Module Registers 3 EMAC Control Module Registers Table 9 lists the memory-mapped registers for the EMAC control module. See the device-specific data manual for the memory address of these registers. Table 9. EMAC Control Module Registers Slave VBUS Address Acronym 3.1 Register Description Section 0h CMIDVER Identification and Version Register Section 3.1 4h CMSOFTRESET Software Reset Register Section 3.2 8h CMEMCONTROL Emulation Control Register Section 3.
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www.ti.com EMAC Control Module Registers 3.2 EMAC Control Module Software Reset Register (CMSOFTRESET) The software reset register (CMSOFTRESET) is shown in Figure 14 and described in Table 11. Figure 14. EMAC Control Module Software Reset Register (CMSOFTRESET) 31 16 Reserved R-0 15 1 0 Reserved SOFTRESET R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 11. EMAC Control Module Software Reset Register (CMSOFTRESET) Field Descriptions Bit 31-1 0 3.
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www.ti.com EMAC Control Module Registers 3.4 EMAC Control Module Interrupt Control Register (CMINTCTRL) The interrupt control register (CMINTCTRL) is shown in Figure 16 and described in Table 13. Figure 16. EMAC Control Module Interrupt Control Register (CMINTCTRL) 31 30 18 17 16 Reserved Reserved INTPACEEN R/W-0 R-0 R/W-0 15 12 11 0 Reserved INTPRESCALE R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 13.
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www.ti.com EMAC Control Module Registers 3.5 EMAC Control Module Receive Threshold Interrupt Enable Register (CMRXTHRESHINTEN) The receive threshold interrupt enable register (CMRXTHRESHINTEN) is shown in Figure 17 and described in Table 14. Figure 17. EMAC Control Module Receive Threshold Interrupt Enable Register (CMRXTHRESHINTEN) 31 16 Reserved R-0 15 8 7 0 Reserved RXTHRESHEN R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 14.
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www.ti.com EMAC Control Module Registers 3.7 EMAC Control Module Transmit Interrupt Enable Register (CMTXINTEN) The transmit interrupt enable register (CMTXINTEN) is shown in Figure 19 and described in Table 16. Figure 19. EMAC Control Module Transmit Interrupt Enable Register (CMTXINTEN) 31 16 Reserved R-0 15 8 7 0 Reserved TXPULSEEN R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 16.
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www.ti.com EMAC Control Module Registers 3.8 EMAC Control Module Miscellaneous Interrupt Enable Register (CMMISCINTEN) The miscellaneous interrupt enable register (CMMISCINTEN) is shown in Figure 20 and described in Table 17. Figure 20.
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www.ti.com EMAC Control Module Registers 3.9 EMAC Control Module Receive Threshold Interrupt Status Register (CMRXTHRESHINTSTAT) The receive threshold interrupt status register (CMRXTHRESHINTSTAT) is shown in Figure 21 and described in Table 18. Figure 21. EMAC Control Module Receive Threshold Interrupt Status Register (CMRXTHRESHINTSTAT) 31 16 Reserved R-0 15 8 7 0 Reserved RXTHRESHINTTSTAT R-0 R-0 LEGEND: R = Read only; -n = value after reset Table 18.
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www.ti.com EMAC Control Module Registers 3.11 EMAC Control Module Transmit Interrupt Status Register (CMTXINTSTAT) The transmit interrupt status register (CMTXINTSTAT) is shown in Figure 23 and described in Table 20. Figure 23. EMAC Control Module Transmit Interrupt Status Register (CMTXINTSTAT) 31 16 Reserved R-0 15 8 7 0 Reserved TXPULSEINTTSTAT R-0 R-0 LEGEND: R = Read only; -n = value after reset Table 20.
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www.ti.com EMAC Control Module Registers 3.12 EMAC Control Module Miscellaneous Interrupt Status Register (EWMISCSTAT) The miscellaneous interrupt status register (EWMISCSTAT) is shown in Figure 24 and described in Table 21. Figure 24. EMAC Control Module Miscellaneous Interrupt Status Register (CMMISCINTSTAT) 31 16 Reserved R-0 15 3 2 1 0 Reserved 4 STATPENDINTSTAT HOSTPENDINTSTAT LINKINTSTAT USERINTSTAT R-0 R-0 R-0 R-0 R-0 LEGEND: R = Read only; -n = value after reset Table 21.
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www.ti.com EMAC Control Module Registers 3.13 EMAC Control Module Receive Interrupts per Millisecond Register (CMRXINTMAX) The receive interrupts per millisecond register (CMRXINTMAX) is shown in Figure 25and described in Table 22. Figure 25. EMAC Control Module Receive Interrupts per Millisecond Register (CMRXINTMAX) 31 16 Reserved R-0 15 6 5 0 Reserved RXIMAX R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 22.
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www.ti.com MDIO Registers 4 MDIO Registers Table 24 lists the memory-mapped registers for the MDIO module. See the device-specific data manual for the memory address of these registers. Table 24. Management Data Input/Output (MDIO) Registers 4.1 Offset Acronym Register Description Section 0h VERSION MDIO Version Register Section 4.1 4h CONTROL MDIO Control Register Section 4.2 8h ALIVE PHY Alive Status register Section 4.3 Ch LINK PHY Link Status Register Section 4.
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www.ti.com MDIO Registers 4.2 MDIO Control Register (CONTROL) The MDIO control register (CONTROL) is shown in Figure 28 and described in Table 26. Figure 28.
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www.ti.com MDIO Registers 4.3 PHY Acknowledge Status Register (ALIVE) The PHY acknowledge status register (ALIVE) is shown in Figure 29 and described in Table 27. Figure 29. PHY Acknowledge Status Register (ALIVE) 31 16 ALIVE R/W1C-0 15 0 ALIVE R/W1C-0 LEGEND: R/W = Read/Write; W1C = Write 1 to clear, write of 0 has no effect; -n = value after reset Table 27. PHY Acknowledge Status Register (ALIVE) Field Descriptions Bit Field Value 31-0 ALIVE 0-FFFF FFFFh 4.4 Description MDIO Alive bits.
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www.ti.com MDIO Registers 4.5 MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) The MDIO link status change interrupt (unmasked) register (LINKINTRAW) is shown in Figure 31 and described in Table 29. Figure 31. MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) 31 16 Reserved R-0 15 2 1 0 Reserved LINKINTRAW R-0 R/W1C-0 LEGEND: R = Read only; R/W = Read/Write; W1C = Write 1 to clear, write of 0 has no effect; -n = value after reset Table 29.
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www.ti.com MDIO Registers 4.6 MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) The MDIO link status change interrupt (masked) register (LINKINTMASKED) is shown in Figure 32 and described in Table 30. Figure 32. MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) 31 16 Reserved R-0 15 2 1 0 Reserved LINKINTMASKED R-0 R/W1C-0 LEGEND: R = Read only; R/W = Read/Write; W1C = Write 1 to clear, write of 0 has no effect; -n = value after reset Table 30.
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www.ti.com MDIO Registers 4.7 MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) The MDIO user command complete interrupt (unmasked) register (USERINTRAW) is shown in Figure 33 and described in Table 31. Figure 33. MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) 31 16 Reserved R-0 15 2 1 0 Reserved USERINTRAW R-0 R/W1C-0 LEGEND: R = Read only; R/W = Read/Write; W1C = Write 1 to clear, write of 0 has no effect; -n = value after reset Table 31.
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www.ti.com MDIO Registers 4.8 MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) The MDIO user command complete interrupt (masked) register (USERINTMASKED) is shown in Figure 34 and described in Table 32. Figure 34. MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) 31 16 Reserved R-0 15 2 1 0 Reserved USERINTMASKED R-0 R/W1C-0 LEGEND: R = Read only; R/W = Read/Write; W1C = Write 1 to clear, write of 0 has no effect; -n = value after reset Table 32.
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www.ti.com MDIO Registers 4.9 MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) The MDIO user command complete interrupt mask set register (USERINTMASKSET) is shown in Figure 35 and described in Table 33. Figure 35. MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) 31 16 Reserved R-0 15 2 1 0 Reserved USERINTMASKSET R-0 R/W1S-0 LEGEND: R = Read only; R/W = Read/Write; W1S = Write 1 to set, write of 0 has no effect; -n = value after reset Table 33.
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www.ti.com MDIO Registers 4.10 MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) The MDIO user command complete interrupt mask clear register (USERINTMASKCLEAR) is shown in Figure 36 and described in Table 34. Figure 36.
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www.ti.com MDIO Registers 4.11 MDIO User Access Register 0 (USERACCESS0) The MDIO user access register 0 (USERACCESS0) is shown in Figure 37 and described in Table 35. Figure 37. MDIO User Access Register 0 (USERACCESS0) 31 30 29 GO WRITE ACK 28 Reserved 26 25 REGADR 21 20 PHYADR 16 R/W1S-0 R/W-0 R/W-0 R-0 R/W-0 R/W-0 15 0 DATA R/W-0 LEGEND: R = Read only; R/W = Read/Write; W1S = Write 1 to set, write of 0 has no effect; -n = value after reset Table 35.
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www.ti.com MDIO Registers 4.12 MDIO User PHY Select Register 0 (USERPHYSEL0) The MDIO user PHY select register 0 (USERPHYSEL0) is shown in Figure 38 and described in Table 36. Figure 38. MDIO User PHY Select Register 0 (USERPHYSEL0) 31 16 Reserved R-0 15 7 6 5 Reserved 8 LINKSEL LINKINTENB Rsvd 4 PHYADRMON 0 R-0 R/W-0 R/W-0 R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 36.
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www.ti.com MDIO Registers 4.13 MDIO User Access Register 1 (USERACCESS1) The MDIO user access register 1 (USERACCESS1) is shown in Figure 39 and described in Table 37. Figure 39. MDIO User Access Register 1 (USERACCESS1) 31 30 29 GO WRITE ACK 28 Reserved 26 25 REGADR 21 20 PHYADR 16 R/W1S-0 R/W-0 R/W-0 R-0 R/W-0 R/W-0 15 0 DATA R/W-0 LEGEND: R = Read only; R/W = Read/Write; W1S = Write 1 to set, write of 0 has no effect; -n = value after reset Table 37.
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www.ti.com MDIO Registers 4.14 MDIO User PHY Select Register 1 (USERPHYSEL1) The MDIO user PHY select register 1 (USERPHYSEL1) is shown in Figure 40 and described in Table 38. Figure 40. MDIO User PHY Select Register 1 (USERPHYSEL1) 31 16 Reserved R-0 15 7 6 5 Reserved 8 LINKSEL LINKINTENB Rsvd 4 PHYADRMON 0 R-0 R/W-0 R/W-0 R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 38.
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www.ti.com Ethernet Media Access Controller (EMAC) Registers 5 Ethernet Media Access Controller (EMAC) Registers Table 39 lists the memory-mapped registers for the EMAC. See the device-specific data manual for the memory address of these registers. Table 39. Ethernet Media Access Controller (EMAC) Registers 84 Offset Acronym Register Description Section 0h TXIDVER Transmit Identification and Version Register Section 5.1 4h TXCONTROL Transmit Control Register Section 5.
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www.ti.com Ethernet Media Access Controller (EMAC) Registers Table 39. Ethernet Media Access Controller (EMAC) Registers (continued) Offset Acronym Register Description Section 164h MACSTATUS MAC Status Register Section 5.30 168h EMCONTROL Emulation Control Register Section 5.31 16Ch FIFOCONTROL FIFO Control Register Section 5.32 170h MACCONFIG MAC Configuration Register Section 5.33 174h SOFTRESET Soft Reset Register Section 5.
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www.ti.com Ethernet Media Access Controller (EMAC) Registers Table 39. Ethernet Media Access Controller (EMAC) Registers (continued) Offset Acronym Register Description 678h RX6CP Receive Channel 6 Completion Pointer Register Section 5.49 Section 67Ch RX7CP Receive Channel 7 Completion Pointer Register Section 5.49 Network Statistics Registers 86 200h RXGOODFRAMES Good Receive Frames Register Section 5.50.1 204h RXBCASTFRAMES Broadcast Receive Frames Register Section 5.50.
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www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.1 Transmit Identification and Version Register (TXIDVER) The transmit identification and version register (TXIDVER) is shown in Figure 41 and described in Table 40. Figure 41. Transmit Identification and Version Register (TXIDVER) 31 16 TXIDENT R-0Ch 15 8 7 0 TXMAJORVER TXMINORVER R-0Ah R-07h LEGEND: R = Read only; -n = value after reset Table 40.
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www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.3 Transmit Teardown Register (TXTEARDOWN) The transmit teardown register (TXTEARDOWN) is shown in Figure 43 and described in Table 42. Figure 43. Transmit Teardown Register (TXTEARDOWN) 31 16 Reserved R-0 15 3 2 0 Reserved TXTDNCH R-0 R/W-0 LEGEND: R = Read only; R/W = Read/Write; -n = value after reset Table 42.
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www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.4 Receive Identification and Version Register (RXIDVER) The receive identification and version register (RXIDVER) is shown in Figure 44 and described in Table 43. Figure 44. Receive Identification and Version Register (RXIDVER) 31 16 RXIDENT R-0Ch 15 8 7 0 RXMAJORVER RXMINORVER R-0Ah R-07h LEGEND: R = Read only; -n = value after reset Table 43.
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www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.6 Receive Teardown Register (RXTEARDOWN) The receive teardown register (RXTEARDOWN) is shown in Figure 46 and described in Table 45. Figure 46. Receive Teardown Register (RXTEARDOWN) 31 16 Reserved R-0 15 3 2 0 Reserved RXTDNCH R-0 R/W-0 LEGEND: R = Read only; R/W = Read/Write; -n = value after reset Table 45.
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www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.7 Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) The transmit interrupt status (unmasked) register (TXINTSTATRAW) is shown in Figure 47 and described in Table 46. Figure 47.
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www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.8 Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) The transmit interrupt status (masked) register (TXINTSTATMASKED) is shown in Figure 48 and described in Table 47. Figure 48.
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www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.9 Transmit Interrupt Mask Set Register (TXINTMASKSET) The transmit interrupt mask set register (TXINTMASKSET) is shown in Figure 49 and described in Table 48. Figure 49.
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www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.10 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) The transmit interrupt mask clear register (TXINTMASKCLEAR) is shown in Figure 50 and described in Table 49. Figure 50.
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www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.11 MAC Input Vector Register (MACINVECTOR) The MAC input vector register (MACINVECTOR) is shown in Figure 51 and described in Table 50. Figure 51. MAC Input Vector Register (MACINVECTOR) 31 27 26 25 24 Reserved 28 STATPEND HOSTPEND LINKINT USERINT TXPEND R-0 R-0 R-0 R-0 R-0 R-0 15 23 8 16 7 0 RXTHRESHPEND RXPEND R-0 R-0 LEGEND: R = Read only; -n = value after reset Table 50.
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www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.13 Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) The receive interrupt status (unmasked) register (RXINTSTATRAW) is shown in Figure 53 and described in Table 52. Figure 53.
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www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.14 Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) The receive interrupt status (masked) register (RXINTSTATMASKED) is shown in Figure 54 and described in Table 53. Figure 54.
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www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.15 Receive Interrupt Mask Set Register (RXINTMASKSET) The receive interrupt mask set register (RXINTMASKSET) is shown in Figure 55 and described in Table 54. Figure 55.
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www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.16 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) The receive interrupt mask clear register (RXINTMASKCLEAR) is shown in Figure 56 and described in Table 55. Figure 56.
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www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.17 MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) The MAC interrupt status (unmasked) register (MACINTSTATRAW) is shown in Figure 57 and described in Table 56. Figure 57. MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) 31 16 Reserved R-0 15 1 0 Reserved 2 HOSTPEND STATPEND R-0 R-0 R-0 LEGEND: R = Read only; -n = value after reset Table 56.
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www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.19 MAC Interrupt Mask Set Register (MACINTMASKSET) The MAC interrupt mask set register (MACINTMASKSET) is shown in Figure 59 and described in Table 58. Figure 59. MAC Interrupt Mask Set Register (MACINTMASKSET) 31 16 Reserved R-0 15 1 0 Reserved 2 HOSTMASK STATMASK R-0 R/W1S-0 R/W1S-0 LEGEND: R = Read only; R/W = Read/Write; W1S = Write 1 to set, write of 0 has no effect; -n = value after reset Table 58.
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www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.21 Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) The receive multicast/broadcast/promiscuous channel enable register (RXMBPENABLE) is shown in Figure 61 and described in Table 60. Figure 61.
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www.ti.com Ethernet Media Access Controller (EMAC) Registers Table 60. Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) Field Descriptions (continued) Bit Field 22 RXCEFEN 21 Reserved 18-16 RXPROMCH 13 10-8 RXBROADCH 5 4-3 Frames containing errors are filtered. 1 Frames containing errors are transferred to memory. 0 Frames that do not address match are filtered.
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www.ti.com Ethernet Media Access Controller (EMAC) Registers Table 60.
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www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.22 Receive Unicast Enable Set Register (RXUNICASTSET) The receive unicast enable set register (RXUNICASTSET) is shown in Figure 62 and described in Table 61. Figure 62.
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www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.23 Receive Unicast Clear Register (RXUNICASTCLEAR) The receive unicast clear register (RXUNICASTCLEAR) is shown in Figure 63 and described in Table 62. Figure 63.
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www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.24 Receive Maximum Length Register (RXMAXLEN) The receive maximum length register (RXMAXLEN) is shown in Figure 64 and described in Table 63. Figure 64. Receive Maximum Length Register (RXMAXLEN) 31 16 Reserved R-0 15 0 RXMAXLEN R/W-1518 LEGEND: R = Read only; R/W = Read/Write; -n = value after reset Table 63.
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www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.26 Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) The receive filter low priority frame threshold register (RXFILTERLOWTHRESH) is shown in Figure 66 and described in Table 65. Figure 66. Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) 31 16 Reserved R-0 15 8 7 0 Reserved RXFILTERTHRESH R-0 R/W-0 LEGEND: R = Read only; R/W = Read/Write; -n = value after reset Table 65.
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www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.28 Receive Channel 0-7 Free Buffer Count Register (RXnFREEBUFFER) The receive channel 0-7 free buffer count register (RXnFREEBUFFER) is shown in Figure 68 and described in Table 67. Figure 68. Receive Channel n Free Buffer Count Register (RXnFREEBUFFER) 31 16 Reserved R-0 15 0 RXnFREEBUF WI-0 LEGEND: R = Read only; WI = Write to increment; -n = value after reset Table 67.
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www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.29 MAC Control Register (MACCONTROL) The MAC control register (MACCONTROL) is shown in Figure 69 and described in Table 68. Figure 69.
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www.ti.com Ethernet Media Access Controller (EMAC) Registers Table 68. MAC Control Register (MACCONTROL) Field Descriptions (continued) Bit 5 4 3 Field GMII enable bit. GMII RX and TX are held in reset. 1 GMII RX and TX are enabled for receive and transmit. Transmit flow control enable bit. This bit determines if incoming pause frames are acted upon in full-duplex mode. Incoming pause frames are not acted upon in half-duplex mode, regardless of the TXFLOWEN bit setting.
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www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.30 MAC Status Register (MACSTATUS) The MAC status register (MACSTATUS) is shown in Figure 70 and described in Table 69. Figure 70.
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www.ti.com Ethernet Media Access Controller (EMAC) Registers Table 69. MAC Status Register (MACSTATUS) Field Descriptions (continued) Bit 10-8 7-3 2 1 0 Field RXERRCH Value 0-3h Reserved Receive host error channel. These bits indicate which receive channel the host error occurred on. This field is cleared to 0 on a host read.
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www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.31 Emulation Control Register (EMCONTROL) The emulation control register (EMCONTROL) is shown in Figure 71 and described in Table 70. Figure 71. Emulation Control Register (EMCONTROL) 31 16 Reserved R-0 15 1 0 Reserved 2 SOFT FREE R-0 R/W-0 R/W-0 LEGEND: R = Read only; R/W = Read/Write; -n = value after reset Table 70.
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www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.33 MAC Configuration Register (MACCONFIG) The MAC configuration register (MACCONFIG) is shown in Figure 73 and described in Table 72. Figure 73. MAC Configuration Register (MACCONFIG) 31 24 23 16 TXCELLDEPTH RXCELLDEPTH R-18h R-44h 15 8 7 0 ADDRESSTYPE MACCFIG R-2h R-3h LEGEND: R = Read only; -n = value after reset Table 72.
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www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.35 MAC Source Address Low Bytes Register (MACSRCADDRLO) The MAC source address low bytes register (MACSRCADDRLO) is shown in Figure 75 and described in Table 74. Figure 75. MAC Source Address Low Bytes Register (MACSRCADDRLO) 31 16 Reserved R-0 15 8 7 0 MACSRCADDR0 MACSRCADDR1 R/W-0 R/W-0 LEGEND: R = Read only; R/W = Read/Write; -n = value after reset Table 74.
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www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.37 MAC Hash Address Register 1 (MACHASH1) The MAC hash registers allow group addressed frames to be accepted on the basis of a hash function of the address.
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www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.39 Back Off Test Register (BOFFTEST) The back off test register (BOFFTEST) is shown in Figure 79 and described in Table 78. Figure 79. Back Off Random Number Generator Test Register (BOFFTEST) 31 26 25 16 Reserved RNDNUM R-0 R-0 15 12 11 10 9 0 COLLCOUNT Reserved TXBACKOFF R-0 R-0 R-0 LEGEND: R = Read only; -n = value after reset Table 78.
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www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.41 Receive Pause Timer Register (RXPAUSE) The receive pause timer register (RXPAUSE) is shown in Figure 81 and described in Table 80. Figure 81. Receive Pause Timer Register (RXPAUSE) 31 16 Reserved R-0 15 0 PAUSETIMER R-0 LEGEND: R = Read only; -n = value after reset Table 80.
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www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.43 MAC Address Low Bytes Register (MACADDRLO) The MAC address low bytes register used in address matching (MACADDRLO), is shown in Figure 83 and described in Table 82. Figure 83.
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www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.44 MAC Address High Bytes Register (MACADDRHI) The MAC address high bytes register (MACADDRHI) is shown in Figure 84 and described in Table 83. Figure 84. MAC Address High Bytes Register (MACADDRHI) 31 24 23 16 MACADDR2 MACADDR3 R/W-0 R/W-0 15 8 7 0 MACADDR4 MACADDR5 R/W-0 R/W-0 LEGEND: R/W = Read/Write; -n = value after reset Table 83.
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www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.46 Transmit Channel 0-7 DMA Head Descriptor Pointer Register (TXnHDP) The transmit channel 0-7 DMA head descriptor pointer register (TXnHDP) is shown in Figure 86 and described in Table 85. Figure 86. Transmit Channel n DMA Head Descriptor Pointer Register (TXnHDP) 31 16 TXnHDP R/W-x 15 0 TXnHDP R/W-x LEGEND: R/W = Read/Write; -n = value after reset; -x = value is indeterminate after reset Table 85.
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www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.48 Transmit Channel 0-7 Completion Pointer Register (TXnCP) The transmit channel 0-7 completion pointer register (TXnCP) is shown in Figure 88 and described in Table 87. Figure 88. Transmit Channel n Completion Pointer Register (TXnCP) 31 16 TXnCP R/W-x 15 0 TXnCP R/W-x LEGEND: R/W = Read/Write; -n = value after reset; -x = value is indeterminate after reset Table 87.
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www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.50 Network Statistics Registers The EMAC has a set of statistics that record events associated with frame traffic. The statistics values are cleared to zero 38 clocks after the rising edge of reset. When the GMIIEN bit in the MACCONTROL register is set, all statistics registers (see Figure 90) are write-to-decrement. The value written is subtracted from the register value with the result stored in the register.
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www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.50.4 Pause Receive Frames Register (RXPAUSEFRAMES) The total number of IEEE 802.3X pause frames received by the EMAC (whether acted upon or not). A pause frame is defined as having all of the following: • Contained any unicast, broadcast, or multicast address • Contained the length/type field value 88.
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www.ti.com Ethernet Media Access Controller (EMAC) Registers See Section 2.5.5 for definitions of alignment, code, and CRC errors. Overruns have no effect on this statistic. 5.50.8 Receive Jabber Frames Register (RXJABBER) The total number of jabber frames received on the EMAC.
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www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.50.16 Multicast Transmit Frames Register (TXMCASTFRAMES) The total number of good multicast frames transmitted on the EMAC. A good multicast frame is defined as having all of the following: • Any data or MAC control frame destined for any multicast address other than FF-FF-FF-FF-FF-FFh • Was of any length • Had no late or excessive collisions, no carrier loss, and no underrun 5.50.
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www.ti.com Ethernet Media Access Controller (EMAC) Registers CRC errors have no effect on this statistic. 5.50.21 Transmit Multiple Collision Frames Register (TXMULTICOLL) The total number of frames transmitted on the EMAC that experienced multiple collisions.
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www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.50.26 Transmit Octet Frames Register (TXOCTETS) The total number of bytes in all good frames transmitted on the EMAC. A good frame is defined as having all of the following: • Any data or MAC control frame that was destined for any unicast, broadcast, or multicast address • Was any length • Had no late or excessive collisions, no carrier loss, and no underrun 5.50.
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www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.50.31 Transmit and Receive 512 to 1023 Octet Frames Register (FRAME512T1023) The total number of 512-byte to 1023-byte frames received and transmitted on the EMAC.
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www.ti.com Ethernet Media Access Controller (EMAC) Registers 5.50.35 Receive FIFO or DMA Middle of Frame Overruns Register (RXMOFOVERRUNS) The total number of frames received on the EMAC that had either a FIFO or DMA middle of frame (MOF) overrun.
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www.ti.com Appendix A Appendix A Glossary Broadcast MAC Address— A special Ethernet MAC address used to send data to all Ethernet devices on the local network. The broadcast address is FFh-FFh-FFh-FFh-FFh-FFh. The LSB of the first byte is odd, qualifying it as a group address; however, its value is reserved for broadcast. It is classified separately by the EMAC. Descriptor (Packet Buffer Descriptor)— A small memory structure that describes a larger block of memory in terms of size, location, and state.
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www.ti.com Appendix A Link— The transmission path between any two instances of generic cabling. Multicast MAC Address— A class of MAC address that sends a packet to potentially more than one recipient. A group address is specified by setting the LSB of the first MAC address byte to 1. Thus, 01h-02h-03h-04h-05h-06h is a valid multicast address. Typically, an Ethernet MAC looks for only certain multicast addresses on a network to reduce traffic load.
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